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target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()

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kvm_riscv_reg_id() returns an id encoded with an ulong size, i.e. an u32
size when running TARGET_RISCV32 and u64 when running TARGET_RISCV64.

Rename it to kvm_riscv_reg_id_ulong() to enhance code readability. It'll
be in line with the existing kvm_riscv_reg_id_<size>() helpers.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231208183835.2411523-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-12-08 15:38:35 -03:00 committed by Alistair Francis
parent f25974f46a
commit da14fc74d5
1 changed files with 21 additions and 19 deletions
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40
target/riscv/kvm/kvm-cpu.c
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@ -54,7 +54,7 @@ void riscv_kvm_aplic_request(void *opaque, int irq, int level)
static bool cap_has_mp_state; static bool cap_has_mp_state;
static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type,
uint64_t idx) uint64_t idx)
{ {
uint64_t id = KVM_REG_RISCV | type | idx; uint64_t id = KVM_REG_RISCV | type | idx;
@ -82,15 +82,17 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx)
return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx;
} }
#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ #define RISCV_CORE_REG(env, name) \
KVM_REG_RISCV_CORE_REG(name)) kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \
KVM_REG_RISCV_CORE_REG(name))
#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ #define RISCV_CSR_REG(env, name) \
KVM_REG_RISCV_CSR_REG(name)) kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \
KVM_REG_RISCV_CSR_REG(name))
#define RISCV_CONFIG_REG(env, name) \ #define RISCV_CONFIG_REG(env, name) \
kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, \ kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \
KVM_REG_RISCV_CONFIG_REG(name)) KVM_REG_RISCV_CONFIG_REG(name))
#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \
KVM_REG_RISCV_TIMER_REG(name)) KVM_REG_RISCV_TIMER_REG(name))
@ -216,8 +218,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
/* If we're here we're going to disable the MISA bit */ /* If we're here we're going to disable the MISA bit */
reg = 0; reg = 0;
id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT,
misa_cfg->kvm_reg_id); misa_cfg->kvm_reg_id);
ret = kvm_set_one_reg(cs, id, &reg); ret = kvm_set_one_reg(cs, id, &reg);
if (ret != 0) { if (ret != 0) {
/* /*
@ -378,8 +380,8 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
continue; continue;
} }
id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT,
multi_ext_cfg->kvm_reg_id); multi_ext_cfg->kvm_reg_id);
reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
ret = kvm_set_one_reg(cs, id, &reg); ret = kvm_set_one_reg(cs, id, &reg);
if (ret != 0) { if (ret != 0) {
@ -509,7 +511,7 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
env->pc = reg; env->pc = reg;
for (i = 1; i < 32; i++) { for (i = 1; i < 32; i++) {
uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i);
ret = kvm_get_one_reg(cs, id, &reg); ret = kvm_get_one_reg(cs, id, &reg);
if (ret) { if (ret) {
return ret; return ret;
@ -534,7 +536,7 @@ static int kvm_riscv_put_regs_core(CPUState *cs)
} }
for (i = 1; i < 32; i++) { for (i = 1; i < 32; i++) {
uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i);
reg = env->gpr[i]; reg = env->gpr[i];
ret = kvm_set_one_reg(cs, id, &reg); ret = kvm_set_one_reg(cs, id, &reg);
if (ret) { if (ret) {
@ -810,8 +812,8 @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
struct kvm_one_reg reg; struct kvm_one_reg reg;
int ret; int ret;
reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG,
cbomz_cfg->kvm_reg_id); cbomz_cfg->kvm_reg_id);
reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg);
ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg); ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg);
if (ret != 0) { if (ret != 0) {
@ -832,8 +834,8 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i];
struct kvm_one_reg reg; struct kvm_one_reg reg;
reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT,
multi_ext_cfg->kvm_reg_id); multi_ext_cfg->kvm_reg_id);
reg.addr = (uint64_t)&val; reg.addr = (uint64_t)&val;
ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg); ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg);
if (ret != 0) { if (ret != 0) {
@ -924,8 +926,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
multi_ext_cfg = &kvm_multi_ext_cfgs[i]; multi_ext_cfg = &kvm_multi_ext_cfgs[i];
reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT,
multi_ext_cfg->kvm_reg_id); multi_ext_cfg->kvm_reg_id);
reg_search = bsearch(&reg_id, reglist->reg, reglist->n, reg_search = bsearch(&reg_id, reglist->reg, reglist->n,
sizeof(uint64_t), uint64_cmp); sizeof(uint64_t), uint64_cmp);
if (!reg_search) { if (!reg_search) {