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ppc/ppc405: QOM'ify MAL

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The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <d54a243dff94d95ba30dbcc09c27700a90ade932.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2022-08-17 17:08:29 +02:00 committed by Daniel Henrique Barboza
parent 695bce07dc
commit da116a8aab
5 changed files with 117 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hw/ppc/ppc405.h
View File

@ -244,6 +244,7 @@ struct Ppc405SoCState {
Ppc405OpbaState opba; Ppc405OpbaState opba;
Ppc405PobState pob; Ppc405PobState pob;
Ppc405PlbState plb; Ppc405PlbState plb;
Ppc4xxMalState mal;
}; };
/* PowerPC 405 core */ /* PowerPC 405 core */

17
hw/ppc/ppc405_uc.c
View File

@ -1375,6 +1375,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB); object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB); object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
} }
static void ppc405_reset(void *opaque) static void ppc405_reset(void *opaque)
@ -1385,7 +1387,6 @@ static void ppc405_reset(void *opaque)
static void ppc405_soc_realize(DeviceState *dev, Error **errp) static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{ {
Ppc405SoCState *s = PPC405_SOC(dev); Ppc405SoCState *s = PPC405_SOC(dev);
qemu_irq mal_irqs[4];
CPUPPCState *env; CPUPPCState *env;
SysBusDevice *sbd; SysBusDevice *sbd;
int i; int i;
@ -1503,11 +1504,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
} }
/* MAL */ /* MAL */
mal_irqs[0] = qdev_get_gpio_in(s->uic, 11); object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
mal_irqs[1] = qdev_get_gpio_in(s->uic, 12); object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
mal_irqs[2] = qdev_get_gpio_in(s->uic, 13); if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
mal_irqs[3] = qdev_get_gpio_in(s->uic, 14); return;
ppc4xx_mal_init(env, 4, 2, mal_irqs); }
sbd = SYS_BUS_DEVICE(&s->mal);
for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 11 + i));
}
/* Ethernet */ /* Ethernet */
/* Uses UIC IRQs 9, 15, 17 */ /* Uses UIC IRQs 9, 15, 17 */

145
hw/ppc/ppc4xx_devs.c
View File

@ -459,32 +459,10 @@ enum {
MAL0_RCBS1 = 0x1E1, MAL0_RCBS1 = 0x1E1,
}; };
typedef struct ppc4xx_mal_t ppc4xx_mal_t; static void ppc4xx_mal_reset(DeviceState *dev)
struct ppc4xx_mal_t {
qemu_irq irqs[4];
uint32_t cfg;
uint32_t esr;
uint32_t ier;
uint32_t txcasr;
uint32_t txcarr;
uint32_t txeobisr;
uint32_t txdeir;
uint32_t rxcasr;
uint32_t rxcarr;
uint32_t rxeobisr;
uint32_t rxdeir;
uint32_t *txctpr;
uint32_t *rxctpr;
uint32_t *rcbs;
uint8_t txcnum;
uint8_t rxcnum;
};
static void ppc4xx_mal_reset(void *opaque)
{ {
ppc4xx_mal_t *mal; Ppc4xxMalState *mal = PPC4xx_MAL(dev);
mal = opaque;
mal->cfg = 0x0007C000; mal->cfg = 0x0007C000;
mal->esr = 0x00000000; mal->esr = 0x00000000;
mal->ier = 0x00000000; mal->ier = 0x00000000;
@ -498,10 +476,9 @@ static void ppc4xx_mal_reset(void *opaque)
static uint32_t dcr_read_mal(void *opaque, int dcrn) static uint32_t dcr_read_mal(void *opaque, int dcrn)
{ {
ppc4xx_mal_t *mal; Ppc4xxMalState *mal = opaque;
uint32_t ret; uint32_t ret;
mal = opaque;
switch (dcrn) { switch (dcrn) {
case MAL0_CFG: case MAL0_CFG:
ret = mal->cfg; ret = mal->cfg;
@ -555,13 +532,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
{ {
ppc4xx_mal_t *mal; Ppc4xxMalState *mal = opaque;
mal = opaque;
switch (dcrn) { switch (dcrn) {
case MAL0_CFG: case MAL0_CFG:
if (val & 0x80000000) { if (val & 0x80000000) {
ppc4xx_mal_reset(mal); ppc4xx_mal_reset(DEVICE(mal));
} }
mal->cfg = val & 0x00FFC087; mal->cfg = val & 0x00FFC087;
break; break;
@ -612,57 +588,74 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
} }
} }
void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
qemu_irq irqs[4])
{ {
ppc4xx_mal_t *mal; Ppc4xxMalState *mal = PPC4xx_MAL(dev);
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
int i; int i;
assert(txcnum <= 32 && rxcnum <= 32); if (mal->txcnum > 32 || mal->rxcnum > 32) {
mal = g_malloc0(sizeof(*mal)); error_setg(errp, "invalid TXC/RXC number");
mal->txcnum = txcnum; return;
mal->rxcnum = rxcnum;
mal->txctpr = g_new0(uint32_t, txcnum);
mal->rxctpr = g_new0(uint32_t, rxcnum);
mal->rcbs = g_new0(uint32_t, rxcnum);
for (i = 0; i < 4; i++) {
mal->irqs[i] = irqs[i];
} }
qemu_register_reset(&ppc4xx_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG, mal->txctpr = g_new0(uint32_t, mal->txcnum);
mal, &dcr_read_mal, &dcr_write_mal); mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
ppc_dcr_register(env, MAL0_ESR, mal->rcbs = g_new0(uint32_t, mal->rxcnum);
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_IER, for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
mal, &dcr_read_mal, &dcr_write_mal); sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]);
ppc_dcr_register(env, MAL0_TXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
for (i = 0; i < txcnum; i++) {
ppc_dcr_register(env, MAL0_TXCTP0R + i,
mal, &dcr_read_mal, &dcr_write_mal);
} }
for (i = 0; i < rxcnum; i++) {
ppc_dcr_register(env, MAL0_RXCTP0R + i, ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal);
mal, &dcr_read_mal, &dcr_write_mal); ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
for (i = 0; i < mal->txcnum; i++) {
ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i,
mal, &dcr_read_mal, &dcr_write_mal);
} }
for (i = 0; i < rxcnum; i++) { for (i = 0; i < mal->rxcnum; i++) {
ppc_dcr_register(env, MAL0_RCBS0 + i, ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i,
mal, &dcr_read_mal, &dcr_write_mal); mal, &dcr_read_mal, &dcr_write_mal);
} }
for (i = 0; i < mal->rxcnum; i++) {
ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i,
mal, &dcr_read_mal, &dcr_write_mal);
}
}
static void ppc4xx_mal_finalize(Object *obj)
{
Ppc4xxMalState *mal = PPC4xx_MAL(obj);
g_free(mal->rcbs);
g_free(mal->rxctpr);
g_free(mal->txctpr);
}
static Property ppc4xx_mal_properties[] = {
DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = ppc4xx_mal_realize;
dc->reset = ppc4xx_mal_reset;
/* Reason: only works as function of a ppc4xx SoC */
dc->user_creatable = false;
device_class_set_props(dc, ppc4xx_mal_properties);
} }
/* PPC4xx_DCR_DEVICE */ /* PPC4xx_DCR_DEVICE */
@ -696,6 +689,12 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = { static const TypeInfo ppc4xx_types[] = {
{ {
.name = TYPE_PPC4xx_MAL,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc4xxMalState),
.instance_finalize = ppc4xx_mal_finalize,
.class_init = ppc4xx_mal_class_init,
}, {
.name = TYPE_PPC4xx_DCR_DEVICE, .name = TYPE_PPC4xx_DCR_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE, .parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc4xxDcrDeviceState), .instance_size = sizeof(Ppc4xxDcrDeviceState),

12
hw/ppc/sam460ex.c
View File

@ -280,7 +280,6 @@ static void sam460ex_init(MachineState *machine)
hwaddr ram_sizes[SDRAM_NR_BANKS] = {0}; hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4]; DeviceState *uic[4];
qemu_irq mal_irqs[4];
int i; int i;
PCIBus *pci_bus; PCIBus *pci_bus;
PowerPCCPU *cpu; PowerPCCPU *cpu;
@ -387,10 +386,15 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdr_init(env); ppc4xx_sdr_init(env);
/* MAL */ /* MAL */
for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) { dev = qdev_new(TYPE_PPC4xx_MAL);
mal_irqs[i] = qdev_get_gpio_in(uic[2], 3 + i); qdev_prop_set_uint32(dev, "txc-num", 4);
qdev_prop_set_uint32(dev, "rxc-num", 16);
ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
object_unref(OBJECT(dev));
sbdev = SYS_BUS_DEVICE(dev);
for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) {
sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i));
} }
ppc4xx_mal_init(env, 4, 16, mal_irqs);
/* DMA */ /* DMA */
ppc4xx_dma_init(env, 0x200); ppc4xx_dma_init(env, 0x200);

28
include/hw/ppc/ppc4xx.h
View File

@ -40,9 +40,6 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
hwaddr *ram_sizes, hwaddr *ram_sizes,
int do_init); int do_init);
void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
qemu_irq irqs[4]);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
/* /*
@ -61,4 +58,29 @@ void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
Error **errp); Error **errp);
/* Memory Access Layer (MAL) */
#define TYPE_PPC4xx_MAL "ppc4xx-mal"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
struct Ppc4xxMalState {
Ppc4xxDcrDeviceState parent_obj;
qemu_irq irqs[4];
uint32_t cfg;
uint32_t esr;
uint32_t ier;
uint32_t txcasr;
uint32_t txcarr;
uint32_t txeobisr;
uint32_t txdeir;
uint32_t rxcasr;
uint32_t rxcarr;
uint32_t rxeobisr;
uint32_t rxdeir;
uint32_t *txctpr;
uint32_t *rxctpr;
uint32_t *rcbs;
uint8_t txcnum;
uint8_t rxcnum;
};
#endif /* PPC4XX_H */ #endif /* PPC4XX_H */