hw/char/mcf_uart: QOMify the ColdFire UART
Use type_init() etc. to adapt the ColdFire UART to the latest QEMU device conventions. Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <1485586582-6490-1-git-send-email-huth@tuxfamily.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -7,12 +7,15 @@
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*/
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*/
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "hw/m68k/mcf.h"
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#include "hw/m68k/mcf.h"
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#include "sysemu/char.h"
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#include "sysemu/char.h"
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#include "exec/address-spaces.h"
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#include "exec/address-spaces.h"
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#include "qapi/error.h"
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#include "qapi/error.h"
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typedef struct {
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typedef struct {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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MemoryRegion iomem;
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uint8_t mr[2];
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uint8_t mr[2];
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uint8_t sr;
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uint8_t sr;
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@ -30,6 +33,9 @@ typedef struct {
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CharBackend chr;
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CharBackend chr;
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} mcf_uart_state;
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} mcf_uart_state;
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#define TYPE_MCF_UART "mcf-uart"
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#define MCF_UART(obj) OBJECT_CHECK(mcf_uart_state, (obj), TYPE_MCF_UART)
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/* UART Status Register bits. */
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/* UART Status Register bits. */
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#define MCF_UART_RxRDY 0x01
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#define MCF_UART_RxRDY 0x01
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#define MCF_UART_FFULL 0x02
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#define MCF_UART_FFULL 0x02
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@ -220,8 +226,10 @@ void mcf_uart_write(void *opaque, hwaddr addr,
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mcf_uart_update(s);
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mcf_uart_update(s);
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}
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}
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static void mcf_uart_reset(mcf_uart_state *s)
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static void mcf_uart_reset(DeviceState *dev)
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{
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{
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mcf_uart_state *s = MCF_UART(dev);
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s->fifo_len = 0;
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s->fifo_len = 0;
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s->mr[0] = 0;
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s->mr[0] = 0;
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s->mr[1] = 0;
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s->mr[1] = 0;
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@ -275,36 +283,80 @@ static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size)
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mcf_uart_push_byte(s, buf[0]);
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mcf_uart_push_byte(s, buf[0]);
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}
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}
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void *mcf_uart_init(qemu_irq irq, Chardev *chr)
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{
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mcf_uart_state *s;
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s = g_malloc0(sizeof(mcf_uart_state));
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s->irq = irq;
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if (chr) {
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qemu_chr_fe_init(&s->chr, chr, &error_abort);
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qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive,
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mcf_uart_receive, mcf_uart_event,
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s, NULL, true);
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}
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mcf_uart_reset(s);
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return s;
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}
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static const MemoryRegionOps mcf_uart_ops = {
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static const MemoryRegionOps mcf_uart_ops = {
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.read = mcf_uart_read,
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.read = mcf_uart_read,
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.write = mcf_uart_write,
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.write = mcf_uart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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};
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void mcf_uart_mm_init(MemoryRegion *sysmem,
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static void mcf_uart_instance_init(Object *obj)
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hwaddr base,
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qemu_irq irq,
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Chardev *chr)
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{
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{
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mcf_uart_state *s;
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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mcf_uart_state *s = MCF_UART(dev);
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s = mcf_uart_init(irq, chr);
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memory_region_init_io(&s->iomem, obj, &mcf_uart_ops, s, "uart", 0x40);
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memory_region_init_io(&s->iomem, NULL, &mcf_uart_ops, s, "uart", 0x40);
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sysbus_init_mmio(dev, &s->iomem);
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memory_region_add_subregion(sysmem, base, &s->iomem);
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sysbus_init_irq(dev, &s->irq);
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}
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static void mcf_uart_realize(DeviceState *dev, Error **errp)
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{
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mcf_uart_state *s = MCF_UART(dev);
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qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive, mcf_uart_receive,
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mcf_uart_event, s, NULL, true);
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}
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static Property mcf_uart_properties[] = {
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DEFINE_PROP_CHR("chardev", mcf_uart_state, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mcf_uart_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = mcf_uart_realize;
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dc->reset = mcf_uart_reset;
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dc->props = mcf_uart_properties;
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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}
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static const TypeInfo mcf_uart_info = {
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.name = TYPE_MCF_UART,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(mcf_uart_state),
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.instance_init = mcf_uart_instance_init,
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.class_init = mcf_uart_class_init,
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};
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static void mcf_uart_register(void)
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{
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type_register_static(&mcf_uart_info);
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}
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type_init(mcf_uart_register)
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void *mcf_uart_init(qemu_irq irq, Chardev *chrdrv)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, TYPE_MCF_UART);
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if (chrdrv) {
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qdev_prop_set_chr(dev, "chardev", chrdrv);
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}
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qdev_init_nofail(dev);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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return dev;
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}
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void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chrdrv)
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{
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DeviceState *dev;
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dev = mcf_uart_init(irq, chrdrv);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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}
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}
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@ -255,9 +255,9 @@ static void mcf5208evb_init(MachineState *machine)
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/* Internal peripherals. */
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/* Internal peripherals. */
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pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
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pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
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mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
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mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]);
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mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
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mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
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mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);
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mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
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mcf5208_sys_init(address_space_mem, pic);
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mcf5208_sys_init(address_space_mem, pic);
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@ -4,17 +4,13 @@
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#include "target/m68k/cpu-qom.h"
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#include "target/m68k/cpu-qom.h"
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struct MemoryRegion;
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/* mcf_uart.c */
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/* mcf_uart.c */
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uint64_t mcf_uart_read(void *opaque, hwaddr addr,
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uint64_t mcf_uart_read(void *opaque, hwaddr addr,
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unsigned size);
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unsigned size);
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void mcf_uart_write(void *opaque, hwaddr addr,
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void mcf_uart_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size);
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uint64_t val, unsigned size);
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void *mcf_uart_init(qemu_irq irq, Chardev *chr);
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void *mcf_uart_init(qemu_irq irq, Chardev *chr);
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void mcf_uart_mm_init(struct MemoryRegion *sysmem,
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void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chr);
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hwaddr base,
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qemu_irq irq, Chardev *chr);
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/* mcf_intc.c */
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/* mcf_intc.c */
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qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
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qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
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