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target/riscv: Split out the vill from vtype

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We need not specially process vtype when XLEN changes.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2022-01-20 20:20:42 +08:00 committed by Alistair Francis
parent 4208dc7e9e
commit d96a271a8d
5 changed files with 19 additions and 6 deletions
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1
target/riscv/cpu.h
View File

@ -125,6 +125,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
bool vill;
target_ulong pc;
target_ulong load_res;

3
target/riscv/cpu_helper.c
View File

@ -60,8 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
uint32_t maxsz = vlmax << sew;
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
(maxsz >= 8);
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
FIELD_EX64(env->vtype, VTYPE, VLMUL));

13
target/riscv/csr.c
View File

@ -283,7 +283,18 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
static RISCVException read_vtype(CPURISCVState *env, int csrno,
target_ulong *val)
{
*val = env->vtype;
uint64_t vill;
switch (env->xl) {
case MXL_RV32:
vill = (uint32_t)env->vill << 31;
break;
case MXL_RV64:
vill = (uint64_t)env->vill << 63;
break;
default:
g_assert_not_reached();
}
*val = (target_ulong)vill | env->vtype;
return RISCV_EXCP_NONE;
}

5
target/riscv/machine.c
View File

@ -124,8 +124,8 @@ static bool vector_needed(void *opaque)
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.needed = vector_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
@ -134,6 +134,7 @@ static const VMStateDescription vmstate_vector = {
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
VMSTATE_BOOL(env.vill, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};

3
target/riscv/vector_helper.c
View File

@ -52,7 +52,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
|| (ediv != 0)
|| (reserved != 0)) {
/* only set vill bit. */
env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
env->vill = 1;
env->vtype = 0;
env->vl = 0;
env->vstart = 0;
return 0;