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Hexagon (target/hexagon) add F2_sfrecipa instruction

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Rd32,Pe4 = sfrecipa(Rs32, Rt32)
    Recripocal approx

Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-18-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson 2021-04-08 20:07:45 -05:00 committed by Richard Henderson
parent 85580a6557
commit d934c16d8a
10 changed files with 252 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
target/hexagon/arch.c
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@ -181,12 +181,13 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust,
/* or put Inf in num fixup? */
uint8_t RsV_sign = float32_is_neg(RsV);
uint8_t RtV_sign = float32_is_neg(RtV);
/* Check that RsV is NOT infinite before we overwrite it */
if (!float32_is_infinity(RsV)) {
float_raise(float_flag_divbyzero, fp_status);
}
RsV = infinite_float32(RsV_sign ^ RtV_sign);
RtV = float32_one;
RdV = float32_one;
if (float32_is_infinity(RsV)) {
float_raise(float_flag_divbyzero, fp_status);
}
} else if (float32_is_infinity(RtV)) {
RsV = make_float32(0x80000000 & (RsV ^ RtV));
RtV = float32_one;
@ -279,3 +280,22 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust,
*adjust = PeV;
return ret;
}
const uint8_t recip_lookup_table[128] = {
0x0fe, 0x0fa, 0x0f6, 0x0f2, 0x0ef, 0x0eb, 0x0e7, 0x0e4,
0x0e0, 0x0dd, 0x0d9, 0x0d6, 0x0d2, 0x0cf, 0x0cc, 0x0c9,
0x0c6, 0x0c2, 0x0bf, 0x0bc, 0x0b9, 0x0b6, 0x0b3, 0x0b1,
0x0ae, 0x0ab, 0x0a8, 0x0a5, 0x0a3, 0x0a0, 0x09d, 0x09b,
0x098, 0x096, 0x093, 0x091, 0x08e, 0x08c, 0x08a, 0x087,
0x085, 0x083, 0x080, 0x07e, 0x07c, 0x07a, 0x078, 0x075,
0x073, 0x071, 0x06f, 0x06d, 0x06b, 0x069, 0x067, 0x065,
0x063, 0x061, 0x05f, 0x05e, 0x05c, 0x05a, 0x058, 0x056,
0x054, 0x053, 0x051, 0x04f, 0x04e, 0x04c, 0x04a, 0x049,
0x047, 0x045, 0x044, 0x042, 0x040, 0x03f, 0x03d, 0x03c,
0x03a, 0x039, 0x037, 0x036, 0x034, 0x033, 0x032, 0x030,
0x02f, 0x02d, 0x02c, 0x02b, 0x029, 0x028, 0x027, 0x025,
0x024, 0x023, 0x021, 0x020, 0x01f, 0x01e, 0x01c, 0x01b,
0x01a, 0x019, 0x017, 0x016, 0x015, 0x014, 0x013, 0x012,
0x011, 0x00f, 0x00e, 0x00d, 0x00c, 0x00b, 0x00a, 0x009,
0x008, 0x007, 0x006, 0x005, 0x004, 0x003, 0x002, 0x000,
};

2
target/hexagon/arch.h
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@ -30,4 +30,6 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd,
int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust,
float_status *fp_status);
extern const uint8_t recip_lookup_table[128];
#endif

21
target/hexagon/gen_tcg.h
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@ -195,6 +195,27 @@
#define fGEN_TCG_S4_stored_locked(SHORTCODE) \
do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
/*
* Mathematical operations with more than one definition require
* special handling
*/
/*
* Approximate reciprocal
* r3,p1 = sfrecipa(r0, r1)
*
* The helper packs the 2 32-bit results into a 64-bit value,
* so unpack them into the proper results.
*/
#define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \
gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \
tcg_temp_free_i64(tmp); \
} while (0)
/* Floating point */
#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
gen_helper_conv_sf2df(RddV, cpu_env, RsV)

1
target/hexagon/helper.h
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@ -24,6 +24,7 @@ DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, int)
DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int)
DEF_HELPER_2(commit_store, void, env, int)
DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32)
DEF_HELPER_3(sfrecipa, i64, env, f32, f32)
/* Floating point */
DEF_HELPER_2(conv_sf2df, f64, env, f32)

1
target/hexagon/imported/encode_pp.def
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@ -1028,6 +1028,7 @@ MPY_ENC(F2_sfmin, "1011","ddddd","0","0","0","1","01")
MPY_ENC(F2_sfmpy, "1011","ddddd","0","0","1","0","00")
MPY_ENC(F2_sffixupn, "1011","ddddd","0","0","1","1","00")
MPY_ENC(F2_sffixupd, "1011","ddddd","0","0","1","1","01")
MPY_ENC(F2_sfrecipa, "1011","ddddd","1","1","1","1","ee")
DEF_FIELDROW_DESC32(ICLASS_M" 1100 -------- PP------ --------","[#12] Rd=(Rs,Rt)")
DEF_FIELD32(ICLASS_M" 1100 -------- PP------ --!-----",Mc_tH,"Rt is High") /*Rt high */

16
target/hexagon/imported/float.idef
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@ -146,6 +146,22 @@ Q6INSN(F2_sfimm_n,"Rd32=sfmake(#u10):neg",ATTRIBS(),
})
Q6INSN(F2_sfrecipa,"Rd32,Pe4=sfrecipa(Rs32,Rt32)",ATTRIBS(),
"Reciprocal Approximation for Division",
{
fHIDE(int idx;)
fHIDE(int adjust;)
fHIDE(int mant;)
fHIDE(int exp;)
if (fSF_RECIP_COMMON(RsV,RtV,RdV,adjust)) {
PeV = adjust;
idx = (RtV >> 16) & 0x7f;
mant = (fSF_RECIP_LOOKUP(idx) << 15) | 1;
exp = fSF_BIAS() - (fSF_GETEXP(RtV) - fSF_BIAS()) - 1;
RdV = fMAKESF(fGETBIT(31,RtV),exp,mant);
}
})
Q6INSN(F2_sffixupn,"Rd32=sffixupn(Rs32,Rt32)",ATTRIBS(),
"Fix Up Numerator",
{

37
target/hexagon/op_helper.c
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@ -289,6 +289,43 @@ int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, int32_t M, int32_t CS)
return new_ptr;
}
static float32 build_float32(uint8_t sign, uint32_t exp, uint32_t mant)
{
return make_float32(
((sign & 1) << 31) |
((exp & 0xff) << SF_MANTBITS) |
(mant & ((1 << SF_MANTBITS) - 1)));
}
/*
* sfrecipa, sfinvsqrta have two 32-bit results
* r0,p0=sfrecipa(r1,r2)
* r0,p0=sfinvsqrta(r1)
*
* Since helpers can only return a single value, we pack the two results
* into a 64-bit value.
*/
uint64_t HELPER(sfrecipa)(CPUHexagonState *env, float32 RsV, float32 RtV)
{
int32_t PeV = 0;
float32 RdV;
int idx;
int adjust;
int mant;
int exp;
arch_fpop_start(env);
if (arch_sf_recip_common(&RsV, &RtV, &RdV, &adjust, &env->fp_status)) {
PeV = adjust;
idx = (RtV >> 16) & 0x7f;
mant = (recip_lookup_table[idx] << 15) | 1;
exp = SF_BIAS - (float32_getexp(RtV) - SF_BIAS) - 1;
RdV = build_float32(extract32(RtV, 31, 1), exp, mant);
}
arch_fpop_end(env);
return ((uint64_t)RdV << 32) | PeV;
}
/*
* mem_noshuf
* Section 5.5 of the Hexagon V67 Programmer's Reference Manual

1
tests/tcg/hexagon/Makefile.target
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@ -39,6 +39,7 @@ HEX_TESTS = first
HEX_TESTS += misc
HEX_TESTS += preg_alias
HEX_TESTS += dual_stores
HEX_TESTS += multi_result
HEX_TESTS += mem_noshuf
HEX_TESTS += atomics
HEX_TESTS += fpstuff

82
tests/tcg/hexagon/fpstuff.c
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@ -250,6 +250,87 @@ static void check_dfminmax(void)
check_fpstatus(usr, FPINVF);
}
static void check_recip_exception(void)
{
int result;
int usr;
/*
* Check that sfrecipa doesn't set status bits when
* a NaN with bit 22 non-zero is passed
*/
asm (CLEAR_FPSTATUS
"%0,p0 = sfrecipa(%2, %3)\n\t"
"%1 = usr\n\t"
: "=r"(result), "=r"(usr) : "r"(SF_NaN), "r"(SF_ANY)
: "r2", "p0", "usr");
check32(result, SF_HEX_NAN);
check_fpstatus(usr, 0);
asm (CLEAR_FPSTATUS
"%0,p0 = sfrecipa(%2, %3)\n\t"
"%1 = usr\n\t"
: "=r"(result), "=r"(usr) : "r"(SF_ANY), "r"(SF_NaN)
: "r2", "p0", "usr");
check32(result, SF_HEX_NAN);
check_fpstatus(usr, 0);
asm (CLEAR_FPSTATUS
"%0,p0 = sfrecipa(%2, %2)\n\t"
"%1 = usr\n\t"
: "=r"(result), "=r"(usr) : "r"(SF_NaN)
: "r2", "p0", "usr");
check32(result, SF_HEX_NAN);
check_fpstatus(usr, 0);
/*
* Check that sfrecipa doesn't set status bits when
* a NaN with bit 22 zero is passed
*/
asm (CLEAR_FPSTATUS
"%0,p0 = sfrecipa(%2, %3)\n\t"
"%1 = usr\n\t"
: "=r"(result), "=r"(usr) : "r"(SF_NaN_special), "r"(SF_ANY)
: "r2", "p0", "usr");
check32(result, SF_HEX_NAN);
check_fpstatus(usr, FPINVF);
asm (CLEAR_FPSTATUS
"%0,p0 = sfrecipa(%2, %3)\n\t"
"%1 = usr\n\t"
: "=r"(result), "=r"(usr) : "r"(SF_ANY), "r"(SF_NaN_special)
: "r2", "p0", "usr");
check32(result, SF_HEX_NAN);
check_fpstatus(usr, FPINVF);
asm (CLEAR_FPSTATUS
"%0,p0 = sfrecipa(%2, %2)\n\t"
"%1 = usr\n\t"
: "=r"(result), "=r"(usr) : "r"(SF_NaN_special)
: "r2", "p0", "usr");
check32(result, SF_HEX_NAN);
check_fpstatus(usr, FPINVF);
/*
* Check that sfrecipa properly sets divid-by-zero
*/
asm (CLEAR_FPSTATUS
"%0,p0 = sfrecipa(%2, %3)\n\t"
"%1 = usr\n\t"
: "=r"(result), "=r"(usr) : "r"(0x885dc960), "r"(0x80000000)
: "r2", "p0", "usr");
check32(result, 0x3f800000);
check_fpstatus(usr, FPDBZF);
asm (CLEAR_FPSTATUS
"%0,p0 = sfrecipa(%2, %3)\n\t"
"%1 = usr\n\t"
: "=r"(result), "=r"(usr) : "r"(0x7f800000), "r"(SF_ZERO)
: "r2", "p0", "usr");
check32(result, 0x3f800000);
check_fpstatus(usr, 0);
}
static void check_canonical_NaN(void)
{
int sf_result;
@ -507,6 +588,7 @@ int main()
check_compare_exception();
check_sfminmax();
check_dfminmax();
check_recip_exception();
check_canonical_NaN();
check_float2int_convs();

68
tests/tcg/hexagon/multi_result.c Normal file
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@ -0,0 +1,68 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdio.h>
static int sfrecipa(int Rs, int Rt, int *pred_result)
{
int result;
int predval;
asm volatile("%0,p0 = sfrecipa(%2, %3)\n\t"
"%1 = p0\n\t"
: "+r"(result), "=r"(predval)
: "r"(Rs), "r"(Rt)
: "p0");
*pred_result = predval;
return result;
}
int err;
static void check(int val, int expect)
{
if (val != expect) {
printf("ERROR: 0x%08x != 0x%08x\n", val, expect);
err++;
}
}
static void check_p(int val, int expect)
{
if (val != expect) {
printf("ERROR: 0x%02x != 0x%02x\n", val, expect);
err++;
}
}
static void test_sfrecipa()
{
int res;
int pred_result;
res = sfrecipa(0x04030201, 0x05060708, &pred_result);
check(res, 0x59f38001);
check_p(pred_result, 0x00);
}
int main()
{
test_sfrecipa();
puts(err ? "FAIL" : "PASS");
return err;
}