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target/nios2: Clean up nios2_cpu_do_interrupt

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Split out do_exception and do_iic_irq to handle bulk of the interrupt and
exception processing.  Parameterize the changes required to cpu state.

The status.EH bit, which protects some data against double-faults,
is only present with the MMU.  Several exception cases did not check
for status.EH being set, as required.

The status.IH bit, which had been set by EXCP_IRQ, is exclusive to
the external interrupt controller, which we do not yet implement.
The internal interrupt controller, when the MMU is also present,
sets the status.EH bit.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-33-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-21 08:17:03 -07:00
parent 24ca31346e
commit d8c5521cc4
1 changed files with 44 additions and 97 deletions
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141
target/nios2/helper.c
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@ -29,6 +29,42 @@
#include "semihosting/semihost.h" #include "semihosting/semihost.h"
static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break)
{
CPUNios2State *env = &cpu->env;
CPUState *cs = CPU(cpu);
uint32_t old_status = env->ctrl[CR_STATUS];
uint32_t new_status = old_status;
if ((old_status & CR_STATUS_EH) == 0) {
int r_ea = R_EA, cr_es = CR_ESTATUS;
if (is_break) {
r_ea = R_BA;
cr_es = CR_BSTATUS;
}
env->ctrl[cr_es] = old_status;
env->regs[r_ea] = env->pc + 4;
if (cpu->mmu_present) {
new_status |= CR_STATUS_EH;
}
}
new_status &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_STATUS] = new_status;
env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
CR_EXCEPTION, CAUSE,
cs->exception_index);
env->pc = exception_addr;
}
static void do_iic_irq(Nios2CPU *cpu)
{
do_exception(cpu, cpu->exception_addr, false);
}
void nios2_cpu_do_interrupt(CPUState *cs) void nios2_cpu_do_interrupt(CPUState *cs)
{ {
Nios2CPU *cpu = NIOS2_CPU(cs); Nios2CPU *cpu = NIOS2_CPU(cs);
@ -36,57 +72,20 @@ void nios2_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) { switch (cs->exception_index) {
case EXCP_IRQ: case EXCP_IRQ:
assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE);
qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc);
do_iic_irq(cpu);
env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
env->ctrl[CR_STATUS] |= CR_STATUS_IH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
CR_EXCEPTION, CAUSE,
cs->exception_index);
env->regs[R_EA] = env->pc + 4;
env->pc = cpu->exception_addr;
break; break;
case EXCP_TLBD: case EXCP_TLBD:
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc);
/* Fast TLB miss */
/* Variation from the spec. Table 3-35 of the cpu reference shows
* estatus not being changed for TLB miss but this appears to
* be incorrect. */
env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
CR_EXCEPTION, CAUSE,
cs->exception_index);
env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
do_exception(cpu, cpu->fast_tlb_miss_addr, false);
env->regs[R_EA] = env->pc + 4;
env->pc = cpu->fast_tlb_miss_addr;
} else { } else {
qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc);
/* Double TLB miss */
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
CR_EXCEPTION, CAUSE,
cs->exception_index);
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL;
do_exception(cpu, cpu->exception_addr, false);
env->pc = cpu->exception_addr;
} }
break; break;
@ -94,78 +93,28 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_TLBW: case EXCP_TLBW:
case EXCP_TLBX: case EXCP_TLBX:
qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc);
env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
CR_EXCEPTION, CAUSE,
cs->exception_index);
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
} }
do_exception(cpu, cpu->exception_addr, false);
env->regs[R_EA] = env->pc + 4;
env->pc = cpu->exception_addr;
break; break;
case EXCP_SUPERA: case EXCP_SUPERA:
case EXCP_SUPERI: case EXCP_SUPERI:
case EXCP_SUPERD: case EXCP_SUPERD:
qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc);
do_exception(cpu, cpu->exception_addr, false);
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
env->regs[R_EA] = env->pc + 4;
}
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
CR_EXCEPTION, CAUSE,
cs->exception_index);
env->pc = cpu->exception_addr;
break; break;
case EXCP_ILLEGAL: case EXCP_ILLEGAL:
case EXCP_TRAP: case EXCP_TRAP:
qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc);
do_exception(cpu, cpu->exception_addr, false);
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
env->regs[R_EA] = env->pc + 4;
}
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
CR_EXCEPTION, CAUSE,
cs->exception_index);
env->pc = cpu->exception_addr;
break; break;
case EXCP_BREAK: case EXCP_BREAK:
qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc);
do_exception(cpu, cpu->exception_addr, true);
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS];
env->regs[R_BA] = env->pc + 4;
}
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
CR_EXCEPTION, CAUSE,
cs->exception_index);
env->pc = cpu->exception_addr;
break; break;
case EXCP_SEMIHOST: case EXCP_SEMIHOST:
@ -175,9 +124,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
break; break;
default: default:
cpu_abort(cs, "unhandled exception type=%d\n", cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index);
cs->exception_index);
break;
} }
} }