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target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL

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Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2012-09-25 15:17:59 -07:00
parent d1c04a2ba0
commit d87aaf934f
2 changed files with 32 additions and 57 deletions
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7
target-s390x/insn-data.def
View File

@ -41,12 +41,19 @@
C(0xeb7e, ALGSI, SIY, GIE, m1_64, i2, new, m1_64, add, addu64)
C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64)
/* MULTIPLY */
C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0)
C(0x5c00, M, RX_a, Z, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
C(0xe35c, MFY, RXY_a, GIE, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
/* MULTIPLY HALFWORD */
C(0x4c00, MH, RX_a, Z, r1_o, m2_16s, new, r1_32, mul, 0)
C(0xe37c, MHY, RXY_a, GIE, r1_o, m2_16s, new, r1_32, mul, 0)
/* MULTIPLY HALFWORD IMMEDIATE */
C(0xa70c, MHI, RI_a, Z, r1_o, i2, new, r1_32, mul, 0)
C(0xa70d, MGHI, RI_a, Z, r1_o, i2, r1, 0, mul, 0)
/* MULTIPLY LOGICAL */
C(0xb996, MLR, RRE, Z, r1p1_32u, r2_32u, new, r1_D32, mul, 0)
C(0xe396, ML, RXY_a, Z, r1p1_32u, m2_32u, new, r1_D32, mul, 0)
/* MULTIPLY SINGLE */
C(0xb252, MSR, RRE, Z, r1_o, r2_o, new, r1_32, mul, 0)
C(0x7100, MS, RX_a, Z, r1_o, m2_32s, new, r1_32, mul, 0)

82
target-s390x/translate.c
View File

@ -1624,18 +1624,6 @@ static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
store_reg32_i64(r1, tmp2);
tcg_temp_free_i64(tmp2);
break;
case 0x96: /* ML R1,D2(X2,B2) [RXY] */
tmp2 = tcg_temp_new_i64();
tmp3 = load_reg((r1 + 1) & 15);
tcg_gen_ext32u_i64(tmp3, tmp3);
tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
tcg_gen_mul_i64(tmp2, tmp2, tmp3);
store_reg32_i64((r1 + 1) & 15, tmp2);
tcg_gen_shri_i64(tmp2, tmp2, 32);
store_reg32_i64(r1, tmp2);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
break;
case 0x97: /* DL R1,D2(X2,B2) [RXY] */
/* reg(r1) = reg(r1, r1+1) % ld32(addr) */
/* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
@ -3219,19 +3207,6 @@ static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
store_reg32(r1, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x96: /* MLR R1,R2 [RRE] */
/* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
tmp2 = load_reg(r2);
tmp3 = load_reg((r1 + 1) & 15);
tcg_gen_ext32u_i64(tmp2, tmp2);
tcg_gen_ext32u_i64(tmp3, tmp3);
tcg_gen_mul_i64(tmp2, tmp2, tmp3);
store_reg32_i64((r1 + 1) & 15, tmp2);
tcg_gen_shri_i64(tmp2, tmp2, 32);
store_reg32_i64(r1, tmp2);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
break;
case 0x97: /* DLR R1,R2 [RRE] */
/* reg(r1) = reg(r1, r1+1) % reg(r2) */
/* reg(r1+1) = reg(r1, r1+1) / reg(r2) */
@ -3605,21 +3580,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x1c: /* MR R1,R2 [RR] */
/* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp2 = load_reg(r2);
tmp3 = load_reg((r1 + 1) & 15);
tcg_gen_ext32s_i64(tmp2, tmp2);
tcg_gen_ext32s_i64(tmp3, tmp3);
tcg_gen_mul_i64(tmp2, tmp2, tmp3);
store_reg32_i64((r1 + 1) & 15, tmp2);
tcg_gen_shri_i64(tmp2, tmp2, 32);
store_reg32_i64(r1, tmp2);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
break;
case 0x1d: /* DR R1,R2 [RR] */
insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
@ -3855,23 +3815,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x5c: /* M R1,D2(X2,B2) [RX] */
/* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */
insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
tmp3 = load_reg((r1 + 1) & 15);
tcg_gen_ext32s_i64(tmp2, tmp2);
tcg_gen_ext32s_i64(tmp3, tmp3);
tcg_gen_mul_i64(tmp2, tmp2, tmp3);
store_reg32_i64((r1 + 1) & 15, tmp2);
tcg_gen_shri_i64(tmp2, tmp2, 32);
store_reg32_i64(r1, tmp2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
break;
case 0x5d: /* D R1,D2(X2,B2) [RX] */
insn = ld_code4(env, s->pc);
tmp3 = decode_rx(s, insn, &r1, &x2, &b2, &d2);
@ -4868,6 +4811,15 @@ static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
store_reg32_i64(get_field(f, r1), o->out);
}
static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
{
/* ??? Specification exception: r1 must be even. */
int r1 = get_field(f, r1);
store_reg32_i64((r1 + 1) & 15, o->out);
tcg_gen_shri_i64(o->out, o->out, 32);
store_reg32_i64(r1, o->out);
}
static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
{
tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
@ -4892,6 +4844,22 @@ static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
o->g_in1 = true;
}
static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
{
/* ??? Specification exception: r1 must be even. */
int r1 = get_field(f, r1);
o->in1 = tcg_temp_new_i64();
tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]);
}
static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
{
/* ??? Specification exception: r1 must be even. */
int r1 = get_field(f, r1);
o->in1 = tcg_temp_new_i64();
tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]);
}
static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
{
o->in1 = load_reg(get_field(f, r2));