target/xtensa: add test_mmuhifi_c3 core
test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
parent
1acd90bff2
commit
d848ea7767
@ -4,6 +4,7 @@ obj-y += core-de212.o
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obj-y += core-fsf.o
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obj-y += core-sample_controller.o
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obj-y += core-test_kc705_be.o
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obj-y += core-test_mmuhifi_c3.o
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obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o
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obj-y += xtensa-isa.o
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obj-y += translate.o op_helper.o helper.o cpu.o
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53
target/xtensa/core-test_mmuhifi_c3.c
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53
target/xtensa/core-test_mmuhifi_c3.c
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2019, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/gdbstub.h"
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#include "qemu/host-utils.h"
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#include "core-test_mmuhifi_c3/core-isa.h"
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#include "overlay_tool.h"
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#define xtensa_modules xtensa_modules_test_mmuhifi_c3
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#include "core-test_mmuhifi_c3/xtensa-modules.inc.c"
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static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {
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.name = "test_mmuhifi_c3",
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.options = XTENSA_OPTIONS,
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.gdb_regmap = {
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.reg = {
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#include "core-test_mmuhifi_c3/gdb-config.inc.c"
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}
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},
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.isa_internal = &xtensa_modules,
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.clock_freq_khz = 40000,
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DEFAULT_SECTIONS
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};
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REGISTER_CORE(test_mmuhifi_c3)
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384
target/xtensa/core-test_mmuhifi_c3/core-isa.h
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384
target/xtensa/core-test_mmuhifi_c3/core-isa.h
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@ -0,0 +1,384 @@
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/*
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* Xtensa processor core configuration information.
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*
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* This file is subject to the terms and conditions of version 2.1 of the GNU
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* Lesser General Public License as published by the Free Software Foundation.
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*
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* Copyright (c) 1999-2009 Tensilica Inc.
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*/
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#ifndef _XTENSA_CORE_CONFIGURATION_H
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#define _XTENSA_CORE_CONFIGURATION_H
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/****************************************************************************
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Parameters Useful for Any Code, USER or PRIVILEGED
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****************************************************************************/
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/*
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* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
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* configured, and a value of 0 otherwise. These macros are always defined.
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*/
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/*----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
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#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
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#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
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#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
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#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
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#define XCHAL_HAVE_DEBUG 1 /* debug option */
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#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
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#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
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#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
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#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
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#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
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#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
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#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
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#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
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#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
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#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
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#define XCHAL_HAVE_L32R 1 /* L32R instruction */
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#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
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#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
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#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
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#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
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#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
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#define XCHAL_HAVE_ABS 1 /* ABS instruction */
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/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
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/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
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#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
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#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
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#define XCHAL_HAVE_SPECULATION 0 /* speculation */
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#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
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#define XCHAL_NUM_CONTEXTS 1 /* */
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#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
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#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
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#define XCHAL_HAVE_PRID 1 /* processor ID register */
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#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
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#define XCHAL_HAVE_MP_INTERRUPTS 1 /* interrupt distributor port */
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#define XCHAL_HAVE_MP_RUNSTALL 1 /* core RunStall control port */
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#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
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#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
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#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
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#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
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#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
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#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
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#define XCHAL_HAVE_FP 0 /* floating point pkg */
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#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
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#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
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#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
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#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
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#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
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#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
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#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
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/*----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
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#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
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#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
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/* In T1050, applies to selected core load and store instructions (see ISA): */
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#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
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#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
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#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
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#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
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#define XCHAL_SW_VERSION 800000 /* sw version of this header */
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#define XCHAL_CORE_ID "test_mmuhifi_c3" /* alphanum core name
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(CoreID) set in the Xtensa
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Processor Generator */
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#define XCHAL_CORE_DESCRIPTION "test_mmuhifi_c3"
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#define XCHAL_BUILD_UNIQUE_ID 0x00005A6A /* 22-bit sw build ID */
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/*
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* These definitions describe the hardware targeted by this software.
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*/
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#define XCHAL_HW_CONFIGID0 0xC1B3CBFE /* ConfigID hi 32 bits*/
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#define XCHAL_HW_CONFIGID1 0x10405A6A /* ConfigID lo 32 bits*/
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#define XCHAL_HW_VERSION_NAME "LX3.0.0" /* full version name */
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#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
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#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */
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#define XCHAL_HW_VERSION 230000 /* major*100+minor */
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#define XCHAL_HW_REL_LX3 1
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#define XCHAL_HW_REL_LX3_0 1
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#define XCHAL_HW_REL_LX3_0_0 1
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#define XCHAL_HW_CONFIGID_RELIABLE 1
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/* If software targets a *range* of hardware versions, these are the bounds: */
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#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
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#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */
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#define XCHAL_HW_MIN_VERSION 230000 /* earliest targeted hw */
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#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION 230000 /* latest targeted hw */
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
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#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
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#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
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#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
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#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
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#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
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#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
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#define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */
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/****************************************************************************
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Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
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****************************************************************************/
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#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
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/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
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/* Number of cache sets in log2(lines per way): */
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#define XCHAL_ICACHE_SETWIDTH 8
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#define XCHAL_DCACHE_SETWIDTH 8
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/* Cache set associativity (number of ways): */
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#define XCHAL_ICACHE_WAYS 2
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#define XCHAL_DCACHE_WAYS 2
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/* Cache features: */
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#define XCHAL_ICACHE_LINE_LOCKABLE 0
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#define XCHAL_DCACHE_LINE_LOCKABLE 0
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#define XCHAL_ICACHE_ECC_PARITY 0
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#define XCHAL_DCACHE_ECC_PARITY 0
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/* Cache access size in bytes (affects operation of SICW instruction): */
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#define XCHAL_ICACHE_ACCESS_SIZE 8
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#define XCHAL_DCACHE_ACCESS_SIZE 8
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/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
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#define XCHAL_CA_BITS 4
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/*----------------------------------------------------------------------
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INTERNAL I/D RAM/ROMs and XLMI
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----------------------------------------------------------------------*/
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#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
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#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
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#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
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#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
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#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
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/*----------------------------------------------------------------------
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INTERRUPTS and TIMERS
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
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#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
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#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */
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#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
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#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */
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#define XCHAL_NUM_INTERRUPTS 12 /* number of interrupts */
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#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
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#define XCHAL_NUM_EXTINTERRUPTS 9 /* num of external interrupts */
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#define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
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(not including level zero) */
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#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
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/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
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/* Masks of interrupts at each interrupt level: */
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#define XCHAL_INTLEVEL1_MASK 0x00000FFF
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#define XCHAL_INTLEVEL2_MASK 0x00000000
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#define XCHAL_INTLEVEL3_MASK 0x00000000
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#define XCHAL_INTLEVEL4_MASK 0x00000000
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#define XCHAL_INTLEVEL5_MASK 0x00000000
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#define XCHAL_INTLEVEL6_MASK 0x00000000
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#define XCHAL_INTLEVEL7_MASK 0x00000000
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/* Masks of interrupts at each range 1..n of interrupt levels: */
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#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000FFF
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#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00000FFF
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#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
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#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00000FFF
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#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00000FFF
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#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00000FFF
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#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00000FFF
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/* Level of each interrupt: */
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#define XCHAL_INT0_LEVEL 1
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#define XCHAL_INT1_LEVEL 1
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#define XCHAL_INT2_LEVEL 1
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#define XCHAL_INT3_LEVEL 1
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#define XCHAL_INT4_LEVEL 1
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#define XCHAL_INT5_LEVEL 1
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#define XCHAL_INT6_LEVEL 1
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#define XCHAL_INT7_LEVEL 1
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#define XCHAL_INT8_LEVEL 1
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#define XCHAL_INT9_LEVEL 1
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#define XCHAL_INT10_LEVEL 1
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#define XCHAL_INT11_LEVEL 1
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#define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */
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#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
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/* Type of each interrupt: */
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#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
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#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
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#define XCHAL_INT8_TYPE XTHAL_INTTYPE_TIMER
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#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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/* Masks of interrupts for each type of interrupt: */
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#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFF000
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#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080
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#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000004
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#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00000E3B
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#define XCHAL_INTTYPE_MASK_TIMER 0x00000140
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#define XCHAL_INTTYPE_MASK_NMI 0x00000000
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#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
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/* Interrupt numbers assigned to specific interrupt sources: */
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#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
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#define XCHAL_TIMER1_INTERRUPT 8 /* CCOMPARE1 */
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#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
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#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
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/* Interrupt numbers for levels at which only one interrupt is configured: */
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/* (There are many interrupts each at level(s) 1.) */
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/*
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* External interrupt vectors/levels.
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* These macros describe how Xtensa processor interrupt numbers
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* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
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* map to external BInterrupt<n> pins, for those interrupts
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* configured as external (level-triggered, edge-triggered, or NMI).
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* See the Xtensa processor databook for more details.
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*/
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/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
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#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
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#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
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#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
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#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
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#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
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#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
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#define XCHAL_EXTINT6_NUM 9 /* (intlevel 1) */
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#define XCHAL_EXTINT7_NUM 10 /* (intlevel 1) */
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#define XCHAL_EXTINT8_NUM 11 /* (intlevel 1) */
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/*----------------------------------------------------------------------
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EXCEPTIONS and VECTORS
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----------------------------------------------------------------------*/
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#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
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number: 1 == XEA1 (old)
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2 == XEA2 (new)
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0 == XEAX (extern) */
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#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
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#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00000000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00000500
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0xD0000340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x00000340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000280
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 0 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
||||
140
target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
Normal file
140
target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
Normal file
@ -0,0 +1,140 @@
|
||||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* idx ofs bi sz al targno flags cp typ group name */
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
|
||||
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
|
||||
"03:04:84:b2","03:04:84:a7",0,0,0,0)
|
||||
XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
|
||||
"03:04:94:b2","03:04:94:a7",0,0,0,0)
|
||||
XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
|
||||
"03:04:a4:b2","03:04:a4:a7",0,0,0,0)
|
||||
XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
|
||||
"03:04:b4:b2","03:04:b4:a7",0,0,0,0)
|
||||
XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
|
||||
"03:04:c4:b2","03:04:c4:a7",0,0,0,0)
|
||||
XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
|
||||
"03:04:d4:b2","03:04:d4:a7",0,0,0,0)
|
||||
XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
|
||||
"03:04:e4:b2","03:04:e4:a7",0,0,0,0)
|
||||
XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
|
||||
"03:04:f4:b2","03:04:f4:a7",0,0,0,0)
|
||||
XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
|
||||
"03:04:04:c3","03:04:04:c1",0,0,0,0)
|
||||
XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
|
||||
"03:04:14:c3","03:04:44:c1",0,0,0,0)
|
||||
XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
|
||||
"03:04:24:c3","03:04:84:c1",0,0,0,0)
|
||||
XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
|
||||
"03:04:34:c3","03:04:c4:c1",0,0,0,0)
|
||||
XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
|
||||
XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
|
||||
XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
|
||||
XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
|
||||
XTREG( 62,296,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
|
||||
XTREG( 63,300,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
|
||||
XTREG( 64,304,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 65,308,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG( 68,320,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG( 69,324,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG( 70,328,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG( 71,332,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG( 72,336,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG( 73,340,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG( 74,344, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
|
||||
XTREG( 75,348,12, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG( 76,352,12, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG( 77,356,12, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG( 78,360,12, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG( 80,368, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG( 81,372,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG( 82,376,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG( 83,380,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG( 84,384,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG( 85,388, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG( 86,392,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG( 87,396,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG( 88,400,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG( 89,404,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG( 90,408,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG( 91,412,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
||||
XTREG( 92,416,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
||||
XTREG( 93,420,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
||||
XTREG( 94,424,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
||||
XTREG( 95,428,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
||||
XTREG( 96,432,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
||||
XTREG( 97,436,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
||||
XTREG( 98,440,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
||||
XTREG( 99,444,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
||||
XTREG(100,448,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
||||
XTREG(101,452,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
||||
XTREG(102,456,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
||||
XTREG(103,460,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
||||
XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
||||
XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
||||
XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
||||
XTREG_END
|
||||
36403
target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
Normal file
36403
target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
Normal file
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user