apic: convert debug printf statements to tracepoints
Replace debug printf statements with tracepoints. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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6df40080b0
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48
hw/apic.c
48
hw/apic.c
@ -21,23 +21,7 @@
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#include "qemu-timer.h"
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#include "qemu-timer.h"
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#include "host-utils.h"
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#include "host-utils.h"
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#include "sysbus.h"
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#include "sysbus.h"
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#include "trace.h"
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//#define DEBUG_APIC
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//#define DEBUG_COALESCING
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#ifdef DEBUG_APIC
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#define DPRINTF(fmt, ...) \
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do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_COALESCING
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#define DPRINTF_C(fmt, ...) \
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do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF_C(fmt, ...)
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#endif
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/* APIC Local Vector Table */
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_TIMER 0
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@ -168,8 +152,8 @@ static void apic_local_deliver(APICState *s, int vector)
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uint32_t lvt = s->lvt[vector];
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uint32_t lvt = s->lvt[vector];
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int trigger_mode;
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int trigger_mode;
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DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector,
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trace_apic_local_deliver(vector, (lvt >> 8) & 7);
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(lvt >> 8) & 7);
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if (lvt & APIC_LVT_MASKED)
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if (lvt & APIC_LVT_MASKED)
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return;
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return;
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@ -300,9 +284,9 @@ void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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{
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{
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d"
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trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
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" polarity %d trigger_mode %d\n", __func__, dest, dest_mode,
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polarity, trigger_mode);
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delivery_mode, vector_num, polarity, trigger_mode);
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
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trigger_mode);
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trigger_mode);
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@ -312,7 +296,8 @@ void cpu_set_apic_base(DeviceState *d, uint64_t val)
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{
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val);
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trace_cpu_set_apic_base(val);
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if (!s)
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if (!s)
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return;
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return;
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s->apicbase = (val & 0xfffff000) |
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s->apicbase = (val & 0xfffff000) |
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@ -329,8 +314,8 @@ uint64_t cpu_get_apic_base(DeviceState *d)
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{
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{
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n",
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trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
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s ? (uint64_t)s->apicbase: 0);
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return s ? s->apicbase : 0;
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return s ? s->apicbase : 0;
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}
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}
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@ -402,20 +387,23 @@ static void apic_update_irq(APICState *s)
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void apic_reset_irq_delivered(void)
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void apic_reset_irq_delivered(void)
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{
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{
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DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered);
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trace_apic_reset_irq_delivered(apic_irq_delivered);
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apic_irq_delivered = 0;
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apic_irq_delivered = 0;
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}
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}
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int apic_get_irq_delivered(void)
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int apic_get_irq_delivered(void)
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{
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{
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DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered);
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trace_apic_get_irq_delivered(apic_irq_delivered);
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return apic_irq_delivered;
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return apic_irq_delivered;
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}
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}
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
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{
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{
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apic_irq_delivered += !get_bit(s->irr, vector_num);
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apic_irq_delivered += !get_bit(s->irr, vector_num);
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DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered);
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trace_apic_set_irq(apic_irq_delivered);
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set_bit(s->irr, vector_num);
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set_bit(s->irr, vector_num);
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if (trigger_mode)
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if (trigger_mode)
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@ -769,7 +757,7 @@ static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
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val = 0;
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val = 0;
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break;
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break;
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}
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}
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DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val);
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trace_apic_mem_readl(addr, val);
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return val;
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return val;
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}
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}
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@ -805,7 +793,7 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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}
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}
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s = DO_UPCAST(APICState, busdev.qdev, d);
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s = DO_UPCAST(APICState, busdev.qdev, d);
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DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val);
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trace_apic_mem_writel(addr, val);
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switch(index) {
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switch(index) {
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case 0x02:
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case 0x02:
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12
trace-events
12
trace-events
@ -69,3 +69,15 @@ disable cpu_out(unsigned int addr, unsigned int val) "addr %#x value %u"
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# balloon.c
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# balloon.c
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# Since requests are raised via monitor, not many tracepoints are needed.
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# Since requests are raised via monitor, not many tracepoints are needed.
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disable balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu"
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disable balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu"
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# hw/apic.c
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disable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
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disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d"
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disable cpu_set_apic_base(uint64_t val) "%016"PRIx64""
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disable cpu_get_apic_base(uint64_t val) "%016"PRIx64""
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disable apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
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disable apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
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# coalescing
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disable apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d"
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disable apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d"
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disable apic_set_irq(int apic_irq_delivered) "coalescing %d"
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