target/mips/translate: Expose check_mips_64() to 32-bit mode
To allow compiling 64-bit specific translation code more generically (and removing #ifdef'ry), allow compiling check_mips_64() on 32-bit targets. If ever called on 32-bit, we obviously emit a reserved instruction exception. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
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@ -2971,18 +2971,16 @@ static inline void check_ps(DisasContext *ctx)
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check_cp1_64bitmode(ctx);
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check_cp1_64bitmode(ctx);
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}
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}
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#ifdef TARGET_MIPS64
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/*
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/*
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* This code generates a "reserved instruction" exception if 64-bit
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* This code generates a "reserved instruction" exception if cpu is not
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* instructions are not enabled.
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* 64-bit or 64-bit instructions are not enabled.
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*/
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*/
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void check_mips_64(DisasContext *ctx)
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void check_mips_64(DisasContext *ctx)
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{
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
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if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
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gen_reserved_instruction(ctx);
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gen_reserved_instruction(ctx);
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}
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}
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}
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}
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#endif
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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static inline void check_mvh(DisasContext *ctx)
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static inline void check_mvh(DisasContext *ctx)
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@ -129,9 +129,7 @@ void generate_exception_end(DisasContext *ctx, int excp);
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void gen_reserved_instruction(DisasContext *ctx);
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void gen_reserved_instruction(DisasContext *ctx);
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void check_insn(DisasContext *ctx, uint64_t flags);
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void check_insn(DisasContext *ctx, uint64_t flags);
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#ifdef TARGET_MIPS64
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void check_mips_64(DisasContext *ctx);
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void check_mips_64(DisasContext *ctx);
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#endif
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void check_cp0_enabled(DisasContext *ctx);
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void check_cp0_enabled(DisasContext *ctx);
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void check_cp1_enabled(DisasContext *ctx);
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void check_cp1_enabled(DisasContext *ctx);
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void check_cp1_64bitmode(DisasContext *ctx);
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void check_cp1_64bitmode(DisasContext *ctx);
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