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target/mips/translate: Expose check_mips_64() to 32-bit mode

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To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-12-15 00:54:34 +01:00
parent 311edee771
commit d7efb69382
2 changed files with 3 additions and 7 deletions
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8
target/mips/translate.c
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@ -2971,18 +2971,16 @@ static inline void check_ps(DisasContext *ctx)
check_cp1_64bitmode(ctx);
}
#ifdef TARGET_MIPS64
/*
* This code generates a "reserved instruction" exception if 64-bit
* instructions are not enabled.
* This code generates a "reserved instruction" exception if cpu is not
* 64-bit or 64-bit instructions are not enabled.
*/
void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
gen_reserved_instruction(ctx);
}
}
#endif
#ifndef CONFIG_USER_ONLY
static inline void check_mvh(DisasContext *ctx)

2
target/mips/translate.h
View File

@ -129,9 +129,7 @@ void generate_exception_end(DisasContext *ctx, int excp);
void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
#endif
void check_cp0_enabled(DisasContext *ctx);
void check_cp1_enabled(DisasContext *ctx);
void check_cp1_64bitmode(DisasContext *ctx);