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target/loongarch: Implement vsrln vsran

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This patch includes:
- VSRLN.{B.H/H.W/W.D};
- VSRAN.{B.H/H.W/W.D};
- VSRLNI.{B.H/H.W/W.D/D.Q};
- VSRANI.{B.H/H.W/W.D/D.Q}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-26-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:51 +08:00
parent ecb9371675
commit d79fb8ddcd
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
5 changed files with 179 additions and 0 deletions
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16
target/loongarch/disas.c
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@ -1166,3 +1166,19 @@ INSN_LSX(vsrari_b, vv_i)
INSN_LSX(vsrari_h, vv_i)
INSN_LSX(vsrari_w, vv_i)
INSN_LSX(vsrari_d, vv_i)
INSN_LSX(vsrln_b_h, vvv)
INSN_LSX(vsrln_h_w, vvv)
INSN_LSX(vsrln_w_d, vvv)
INSN_LSX(vsran_b_h, vvv)
INSN_LSX(vsran_h_w, vvv)
INSN_LSX(vsran_w_d, vvv)
INSN_LSX(vsrlni_b_h, vv_i)
INSN_LSX(vsrlni_h_w, vv_i)
INSN_LSX(vsrlni_w_d, vv_i)
INSN_LSX(vsrlni_d_q, vv_i)
INSN_LSX(vsrani_b_h, vv_i)
INSN_LSX(vsrani_h_w, vv_i)
INSN_LSX(vsrani_w_d, vv_i)
INSN_LSX(vsrani_d_q, vv_i)

16
target/loongarch/helper.h
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@ -379,3 +379,19 @@ DEF_HELPER_4(vsrari_b, void, env, i32, i32, i32)
DEF_HELPER_4(vsrari_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrari_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrari_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrln_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrln_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrln_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsran_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsran_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsran_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlni_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_d_q, void, env, i32, i32, i32)

16
target/loongarch/insn_trans/trans_lsx.c.inc
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@ -3005,3 +3005,19 @@ TRANS(vsrari_b, gen_vv_i, gen_helper_vsrari_b)
TRANS(vsrari_h, gen_vv_i, gen_helper_vsrari_h)
TRANS(vsrari_w, gen_vv_i, gen_helper_vsrari_w)
TRANS(vsrari_d, gen_vv_i, gen_helper_vsrari_d)
TRANS(vsrln_b_h, gen_vvv, gen_helper_vsrln_b_h)
TRANS(vsrln_h_w, gen_vvv, gen_helper_vsrln_h_w)
TRANS(vsrln_w_d, gen_vvv, gen_helper_vsrln_w_d)
TRANS(vsran_b_h, gen_vvv, gen_helper_vsran_b_h)
TRANS(vsran_h_w, gen_vvv, gen_helper_vsran_h_w)
TRANS(vsran_w_d, gen_vvv, gen_helper_vsran_w_d)
TRANS(vsrlni_b_h, gen_vv_i, gen_helper_vsrlni_b_h)
TRANS(vsrlni_h_w, gen_vv_i, gen_helper_vsrlni_h_w)
TRANS(vsrlni_w_d, gen_vv_i, gen_helper_vsrlni_w_d)
TRANS(vsrlni_d_q, gen_vv_i, gen_helper_vsrlni_d_q)
TRANS(vsrani_b_h, gen_vv_i, gen_helper_vsrani_b_h)
TRANS(vsrani_h_w, gen_vv_i, gen_helper_vsrani_h_w)
TRANS(vsrani_w_d, gen_vv_i, gen_helper_vsrani_w_d)
TRANS(vsrani_d_q, gen_vv_i, gen_helper_vsrani_d_q)

17
target/loongarch/insns.decode
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@ -503,6 +503,7 @@ dbcl 0000 00000010 10101 ............... @i15
@vv_ui4 .... ........ ..... . imm:4 vj:5 vd:5 &vv_i
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
@vv_ui6 .... ........ .... imm:6 vj:5 vd:5 &vv_i
@vv_ui7 .... ........ ... imm:7 vj:5 vd:5 &vv_i
@vv_ui8 .... ........ .. imm:8 vj:5 vd:5 &vv_i
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
@ -866,3 +867,19 @@ vsrari_b 0111 00101010 10000 01 ... ..... ..... @vv_ui3
vsrari_h 0111 00101010 10000 1 .... ..... ..... @vv_ui4
vsrari_w 0111 00101010 10001 ..... ..... ..... @vv_ui5
vsrari_d 0111 00101010 1001 ...... ..... ..... @vv_ui6
vsrln_b_h 0111 00001111 01001 ..... ..... ..... @vvv
vsrln_h_w 0111 00001111 01010 ..... ..... ..... @vvv
vsrln_w_d 0111 00001111 01011 ..... ..... ..... @vvv
vsran_b_h 0111 00001111 01101 ..... ..... ..... @vvv
vsran_h_w 0111 00001111 01110 ..... ..... ..... @vvv
vsran_w_d 0111 00001111 01111 ..... ..... ..... @vvv
vsrlni_b_h 0111 00110100 00000 1 .... ..... ..... @vv_ui4
vsrlni_h_w 0111 00110100 00001 ..... ..... ..... @vv_ui5
vsrlni_w_d 0111 00110100 0001 ...... ..... ..... @vv_ui6
vsrlni_d_q 0111 00110100 001 ....... ..... ..... @vv_ui7
vsrani_b_h 0111 00110101 10000 1 .... ..... ..... @vv_ui4
vsrani_h_w 0111 00110101 10001 ..... ..... ..... @vv_ui5
vsrani_w_d 0111 00110101 1001 ...... ..... ..... @vv_ui6
vsrani_d_q 0111 00110101 101 ....... ..... ..... @vv_ui7

114
target/loongarch/lsx_helper.c
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@ -938,3 +938,117 @@ VSRARI(vsrari_b, 8, B)
VSRARI(vsrari_h, 16, H)
VSRARI(vsrari_w, 32, W)
VSRARI(vsrari_d, 64, D)
#define R_SHIFT(a, b) (a >> b)
#define VSRLN(NAME, BIT, T, E1, E2) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t vk) \
{ \
int i; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
VReg *Vk = &(env->fpr[vk].vreg); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
Vd->E1(i) = R_SHIFT((T)Vj->E2(i),((T)Vk->E2(i)) % BIT); \
} \
Vd->D(1) = 0; \
}
VSRLN(vsrln_b_h, 16, uint16_t, B, H)
VSRLN(vsrln_h_w, 32, uint32_t, H, W)
VSRLN(vsrln_w_d, 64, uint64_t, W, D)
#define VSRAN(NAME, BIT, T, E1, E2) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t vk) \
{ \
int i; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
VReg *Vk = &(env->fpr[vk].vreg); \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
Vd->E1(i) = R_SHIFT(Vj->E2(i), ((T)Vk->E2(i)) % BIT); \
} \
Vd->D(1) = 0; \
}
VSRAN(vsran_b_h, 16, uint16_t, B, H)
VSRAN(vsran_h_w, 32, uint32_t, H, W)
VSRAN(vsran_w_d, 64, uint64_t, W, D)
#define VSRLNI(NAME, BIT, T, E1, E2) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t imm) \
{ \
int i, max; \
VReg temp; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
\
temp.D(0) = 0; \
temp.D(1) = 0; \
max = LSX_LEN/BIT; \
for (i = 0; i < max; i++) { \
temp.E1(i) = R_SHIFT((T)Vj->E2(i), imm); \
temp.E1(i + max) = R_SHIFT((T)Vd->E2(i), imm); \
} \
*Vd = temp; \
}
void HELPER(vsrlni_d_q)(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t imm)
{
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
temp.D(0) = 0;
temp.D(1) = 0;
temp.D(0) = int128_getlo(int128_urshift(Vj->Q(0), imm % 128));
temp.D(1) = int128_getlo(int128_urshift(Vd->Q(0), imm % 128));
*Vd = temp;
}
VSRLNI(vsrlni_b_h, 16, uint16_t, B, H)
VSRLNI(vsrlni_h_w, 32, uint32_t, H, W)
VSRLNI(vsrlni_w_d, 64, uint64_t, W, D)
#define VSRANI(NAME, BIT, E1, E2) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t imm) \
{ \
int i, max; \
VReg temp; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
\
temp.D(0) = 0; \
temp.D(1) = 0; \
max = LSX_LEN/BIT; \
for (i = 0; i < max; i++) { \
temp.E1(i) = R_SHIFT(Vj->E2(i), imm); \
temp.E1(i + max) = R_SHIFT(Vd->E2(i), imm); \
} \
*Vd = temp; \
}
void HELPER(vsrani_d_q)(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t imm)
{
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
temp.D(0) = 0;
temp.D(1) = 0;
temp.D(0) = int128_getlo(int128_rshift(Vj->Q(0), imm % 128));
temp.D(1) = int128_getlo(int128_rshift(Vd->Q(0), imm % 128));
*Vd = temp;
}
VSRANI(vsrani_b_h, 16, B, H)
VSRANI(vsrani_h_w, 32, H, W)
VSRANI(vsrani_w_d, 64, W, D)