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target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree

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Convert the CFINV, XAFLAG and AXFLAG insns to decodetree.
The old decoder handles these in handle_msr_i(), but
the architecture defines them as separate instructions
from MSR (immediate).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-06-19 11:20:20 +01:00
parent afcd5df54c
commit d78b662f28
2 changed files with 32 additions and 27 deletions
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6
target/arm/tcg/a64.decode
View File

@ -188,3 +188,9 @@ CLREX 1101 0101 0000 0011 0011 ---- 010 11111
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
ISB 1101 0101 0000 0011 0011 ---- 110 11111 ISB 1101 0101 0000 0011 0011 ---- 110 11111
SB 1101 0101 0000 0011 0011 0000 111 11111 SB 1101 0101 0000 0011 0011 0000 111 11111
# PSTATE
CFINV 1101 0101 0000 0 000 0100 0000 000 11111
XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111
AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111

53
target/arm/tcg/translate-a64.c
View File

@ -1864,9 +1864,24 @@ static bool trans_SB(DisasContext *s, arg_SB *a)
return true; return true;
} }
static void gen_xaflag(void) static bool trans_CFINV(DisasContext *s, arg_CFINV *a)
{ {
TCGv_i32 z = tcg_temp_new_i32(); if (!dc_isar_feature(aa64_condm_4, s)) {
return false;
}
tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
return true;
}
static bool trans_XAFLAG(DisasContext *s, arg_XAFLAG *a)
{
TCGv_i32 z;
if (!dc_isar_feature(aa64_condm_5, s)) {
return false;
}
z = tcg_temp_new_i32();
tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0);
@ -1890,10 +1905,16 @@ static void gen_xaflag(void)
/* C | Z */ /* C | Z */
tcg_gen_or_i32(cpu_CF, cpu_CF, z); tcg_gen_or_i32(cpu_CF, cpu_CF, z);
return true;
} }
static void gen_axflag(void) static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a)
{ {
if (!dc_isar_feature(aa64_condm_5, s)) {
return false;
}
tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */
tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */
@ -1902,6 +1923,8 @@ static void gen_axflag(void)
tcg_gen_movi_i32(cpu_NF, 0); tcg_gen_movi_i32(cpu_NF, 0);
tcg_gen_movi_i32(cpu_VF, 0); tcg_gen_movi_i32(cpu_VF, 0);
return true;
} }
/* MSR (immediate) - move immediate to processor state field */ /* MSR (immediate) - move immediate to processor state field */
@ -1914,30 +1937,6 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
s->base.is_jmp = DISAS_TOO_MANY; s->base.is_jmp = DISAS_TOO_MANY;
switch (op) { switch (op) {
case 0x00: /* CFINV */
if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) {
goto do_unallocated;
}
tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
s->base.is_jmp = DISAS_NEXT;
break;
case 0x01: /* XAFlag */
if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
goto do_unallocated;
}
gen_xaflag();
s->base.is_jmp = DISAS_NEXT;
break;
case 0x02: /* AXFlag */
if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
goto do_unallocated;
}
gen_axflag();
s->base.is_jmp = DISAS_NEXT;
break;
case 0x03: /* UAO */ case 0x03: /* UAO */
if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) {
goto do_unallocated; goto do_unallocated;