tests/qtest: Adding PCS Module test to GMAC Qtest
- Add PCS Register check to npcm_gmac-test Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12 Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-7-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Nabih Estefan Diaz
Peter Maydell
parent
1c51c57199
commit
d710b33751
@ -23,6 +23,10 @@
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/* Name of the GMAC Device */
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#define TYPE_NPCM_GMAC "npcm-gmac"
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/* Address of the PCS Module */
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#define PCS_BASE_ADDRESS 0xf0780000
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#define NPCM_PCS_IND_AC_BA 0x1fe
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typedef struct GMACModule {
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int irq;
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uint64_t base_addr;
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@ -114,6 +118,62 @@ typedef enum NPCMRegister {
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NPCM_GMAC_PTP_STNSUR = 0x714,
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NPCM_GMAC_PTP_TAR = 0x718,
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NPCM_GMAC_PTP_TTSR = 0x71c,
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/* PCS Registers */
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NPCM_PCS_SR_CTL_ID1 = 0x3c0008,
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NPCM_PCS_SR_CTL_ID2 = 0x3c000a,
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NPCM_PCS_SR_CTL_STS = 0x3c0010,
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NPCM_PCS_SR_MII_CTRL = 0x3e0000,
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NPCM_PCS_SR_MII_STS = 0x3e0002,
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NPCM_PCS_SR_MII_DEV_ID1 = 0x3e0004,
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NPCM_PCS_SR_MII_DEV_ID2 = 0x3e0006,
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NPCM_PCS_SR_MII_AN_ADV = 0x3e0008,
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NPCM_PCS_SR_MII_LP_BABL = 0x3e000a,
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NPCM_PCS_SR_MII_AN_EXPN = 0x3e000c,
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NPCM_PCS_SR_MII_EXT_STS = 0x3e001e,
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NPCM_PCS_SR_TIM_SYNC_ABL = 0x3e0e10,
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NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR = 0x3e0e12,
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NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR = 0x3e0e14,
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NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR = 0x3e0e16,
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NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR = 0x3e0e18,
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NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR = 0x3e0e1a,
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NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR = 0x3e0e1c,
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NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR = 0x3e0e1e,
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NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR = 0x3e0e20,
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NPCM_PCS_VR_MII_MMD_DIG_CTRL1 = 0x3f0000,
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NPCM_PCS_VR_MII_AN_CTRL = 0x3f0002,
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NPCM_PCS_VR_MII_AN_INTR_STS = 0x3f0004,
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NPCM_PCS_VR_MII_TC = 0x3f0006,
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NPCM_PCS_VR_MII_DBG_CTRL = 0x3f000a,
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NPCM_PCS_VR_MII_EEE_MCTRL0 = 0x3f000c,
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NPCM_PCS_VR_MII_EEE_TXTIMER = 0x3f0010,
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NPCM_PCS_VR_MII_EEE_RXTIMER = 0x3f0012,
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NPCM_PCS_VR_MII_LINK_TIMER_CTRL = 0x3f0014,
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NPCM_PCS_VR_MII_EEE_MCTRL1 = 0x3f0016,
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NPCM_PCS_VR_MII_DIG_STS = 0x3f0020,
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NPCM_PCS_VR_MII_ICG_ERRCNT1 = 0x3f0022,
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NPCM_PCS_VR_MII_MISC_STS = 0x3f0030,
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NPCM_PCS_VR_MII_RX_LSTS = 0x3f0040,
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NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 = 0x3f0070,
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NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 = 0x3f0074,
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NPCM_PCS_VR_MII_MP_TX_GENCTRL0 = 0x3f007a,
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NPCM_PCS_VR_MII_MP_TX_GENCTRL1 = 0x3f007c,
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NPCM_PCS_VR_MII_MP_TX_STS = 0x3f0090,
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NPCM_PCS_VR_MII_MP_RX_GENCTRL0 = 0x3f00b0,
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NPCM_PCS_VR_MII_MP_RX_GENCTRL1 = 0x3f00b2,
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NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 = 0x3f00ba,
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NPCM_PCS_VR_MII_MP_MPLL_CTRL0 = 0x3f00f0,
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NPCM_PCS_VR_MII_MP_MPLL_CTRL1 = 0x3f00f2,
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NPCM_PCS_VR_MII_MP_MPLL_STS = 0x3f0110,
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NPCM_PCS_VR_MII_MP_MISC_CTRL2 = 0x3f0126,
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NPCM_PCS_VR_MII_MP_LVL_CTRL = 0x3f0130,
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NPCM_PCS_VR_MII_MP_MISC_CTRL0 = 0x3f0132,
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NPCM_PCS_VR_MII_MP_MISC_CTRL1 = 0x3f0134,
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NPCM_PCS_VR_MII_DIG_CTRL2 = 0x3f01c2,
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NPCM_PCS_VR_MII_DIG_ERRCNT_SEL = 0x3f01c4,
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} NPCMRegister;
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static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
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@ -122,6 +182,15 @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
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return qtest_readl(qts, mod->base_addr + regno);
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}
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static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
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NPCMRegister regno)
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{
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uint32_t write_value = (regno & 0x3ffe00) >> 9;
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qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
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uint32_t read_offset = regno & 0x1ff;
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return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
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}
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/* Check that GMAC registers are reset to default value */
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static void test_init(gconstpointer test_data)
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{
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@ -134,6 +203,11 @@ static void test_init(gconstpointer test_data)
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g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
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} while (0)
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#define CHECK_REG_PCS(regno, value) \
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do { \
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g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
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} while (0)
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CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
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CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
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CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
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@ -183,6 +257,64 @@ static void test_init(gconstpointer test_data)
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CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
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CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
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/* TODO Add registers PCS */
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if (mod->base_addr == 0xf0802000) {
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CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
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CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
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}
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qtest_quit(qts);
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}
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