target-arm: Enable vPMU support under TCG mode
This patch contains several fixes to enable vPMU under TCG mode. It first removes the checking of kvm_enabled() while unsetting ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU under TCG mode. Secondly the PMU node of DT table is now created under TCG. The last fix is to disable the masking of PMUver field of ID_AA64DFR0_EL1. Signed-off-by: Wei Huang <wei@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1486504171-26807-5-git-send-email-wei@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -471,7 +471,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
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CPU_FOREACH(cpu) {
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armcpu = ARM_CPU(cpu);
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if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) ||
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!kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) {
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(kvm_enabled() && !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ)))) {
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return;
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}
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}
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@ -781,7 +781,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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unset_feature(env, ARM_FEATURE_EL2);
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}
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if (!cpu->has_pmu || !kvm_enabled()) {
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if (!cpu->has_pmu) {
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cpu->has_pmu = false;
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unset_feature(env, ARM_FEATURE_PMU);
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}
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@ -4633,12 +4633,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST,
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/* We mask out the PMUVer field, because we don't currently
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* implement the PMU. Not advertising it prevents the guest
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* from trying to use it and getting UNDEFs on registers we
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* don't implement.
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*/
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.resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
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.resetvalue = cpu->id_aa64dfr0 },
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{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
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.access = PL1_R, .type = ARM_CP_CONST,
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