Add support for variable-length ISAs
-----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAlzQfE0dHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV81RAf8Crg7XVTrZuFEaZC/ 9Sslz1gIYzKinSGj98RFbokd/YiK3G/ouYfdhRrrYwcWL8rt10zR6Bb7ctYhPORo u2agxubSSOcEjy0Rxgok8cbPuBffP3R+3zL7aEPv/wtPKcLFQlxn3cpImhBg7VTL apaIDjFuGRVhvfRtiIo2nJ9wIgzT1hvOZNgLRA4gVZul/U92fotNRQm1PdaWq7fM i76Luk0g69mczvYj40sB+crwQ6cvnCNPqvMl5H//6e3Xc1OolUm5ClzchaLwdThz oqmDchYyBY3vzL2ilZX4cdoQH2tDBbic4IjwNc8U2uUhJSTsxOY7TLhCCODlAX+T pl4GNA== =qpX9 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190506' into staging Add support for variable-length ISAs # gpg: Signature made Mon 06 May 2019 19:26:21 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dt-20190506: decodetree: Add DisasContext argument to !function expanders decodetree: Expand a decode_load function decodetree: Initial support for variable-length ISAs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
d6de7fed80
@ -27,6 +27,7 @@ import getopt
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insnwidth = 32
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insnmask = 0xffffffff
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variablewidth = False
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fields = {}
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arguments = {}
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formats = {}
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@ -255,7 +256,7 @@ class FunctionField:
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return self.func + '(' + str(self.base) + ')'
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def str_extract(self):
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return self.func + '(' + self.base.str_extract() + ')'
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return self.func + '(ctx, ' + self.base.str_extract() + ')'
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def __eq__(self, other):
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return self.func == other.func and self.base == other.base
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@ -289,7 +290,7 @@ class Arguments:
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class General:
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"""Common code between instruction formats and instruction patterns"""
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def __init__(self, name, lineno, base, fixb, fixm, udfm, fldm, flds):
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def __init__(self, name, lineno, base, fixb, fixm, udfm, fldm, flds, w):
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self.name = name
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self.file = input_file
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self.lineno = lineno
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@ -299,6 +300,7 @@ class General:
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self.undefmask = udfm
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self.fieldmask = fldm
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self.fields = flds
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self.width = w
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def __str__(self):
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return self.name + ' ' + str_match_bits(self.fixedbits, self.fixedmask)
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@ -316,7 +318,7 @@ class Format(General):
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return decode_function + '_extract_' + self.name
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def output_extract(self):
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output('static void ', self.extract_name(), '(',
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output('static void ', self.extract_name(), '(DisasContext *ctx, ',
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self.base.struct_name(), ' *a, ', insntype, ' insn)\n{\n')
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for n, f in self.fields.items():
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output(' a->', n, ' = ', f.str_extract(), ';\n')
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@ -341,7 +343,8 @@ class Pattern(General):
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arg = self.base.base.name
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output(ind, '/* ', self.file, ':', str(self.lineno), ' */\n')
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if not extracted:
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output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n')
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output(ind, self.base.extract_name(),
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'(ctx, &u.f_', arg, ', insn);\n')
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for n, f in self.fields.items():
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output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n')
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output(ind, 'if (', translate_prefix, '_', self.name,
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@ -352,7 +355,7 @@ class Pattern(General):
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class MultiPattern(General):
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"""Class representing an overlapping set of instruction patterns"""
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def __init__(self, lineno, pats, fixb, fixm, udfm):
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def __init__(self, lineno, pats, fixb, fixm, udfm, w):
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self.file = input_file
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self.lineno = lineno
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self.pats = pats
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@ -360,6 +363,7 @@ class MultiPattern(General):
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self.fixedbits = fixb
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self.fixedmask = fixm
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self.undefmask = udfm
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self.width = w
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def __str__(self):
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r = "{"
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@ -502,7 +506,7 @@ def infer_argument_set(flds):
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return arg
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def infer_format(arg, fieldmask, flds):
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def infer_format(arg, fieldmask, flds, width):
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global arguments
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global formats
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global decode_function
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@ -521,6 +525,8 @@ def infer_format(arg, fieldmask, flds):
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continue
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if fieldmask != fmt.fieldmask:
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continue
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if width != fmt.width:
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continue
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if not eq_fields_for_fmts(flds, fmt.fields):
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continue
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return (fmt, const_flds)
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@ -529,7 +535,7 @@ def infer_format(arg, fieldmask, flds):
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if not arg:
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arg = infer_argument_set(flds)
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fmt = Format(name, 0, arg, 0, 0, 0, fieldmask, var_flds)
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fmt = Format(name, 0, arg, 0, 0, 0, fieldmask, var_flds, width)
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formats[name] = fmt
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return (fmt, const_flds)
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@ -546,6 +552,7 @@ def parse_generic(lineno, is_format, name, toks):
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global re_ident
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global insnwidth
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global insnmask
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global variablewidth
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fixedmask = 0
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fixedbits = 0
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@ -633,8 +640,15 @@ def parse_generic(lineno, is_format, name, toks):
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error(lineno, 'invalid token "{0}"'.format(t))
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width += shift
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if variablewidth and width < insnwidth and width % 8 == 0:
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shift = insnwidth - width
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fixedbits <<= shift
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fixedmask <<= shift
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undefmask <<= shift
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undefmask |= (1 << shift) - 1
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# We should have filled in all of the bits of the instruction.
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if not (is_format and width == 0) and width != insnwidth:
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elif not (is_format and width == 0) and width != insnwidth:
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error(lineno, 'definition has {0} bits'.format(width))
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# Do not check for fields overlaping fields; one valid usage
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@ -660,7 +674,7 @@ def parse_generic(lineno, is_format, name, toks):
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if name in formats:
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error(lineno, 'duplicate format name', name)
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fmt = Format(name, lineno, arg, fixedbits, fixedmask,
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undefmask, fieldmask, flds)
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undefmask, fieldmask, flds, width)
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formats[name] = fmt
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else:
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# Patterns can reference a format ...
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@ -670,12 +684,14 @@ def parse_generic(lineno, is_format, name, toks):
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error(lineno, 'pattern specifies both format and argument set')
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if fixedmask & fmt.fixedmask:
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error(lineno, 'pattern fixed bits overlap format fixed bits')
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if width != fmt.width:
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error(lineno, 'pattern uses format of different width')
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fieldmask |= fmt.fieldmask
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fixedbits |= fmt.fixedbits
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fixedmask |= fmt.fixedmask
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undefmask |= fmt.undefmask
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else:
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(fmt, flds) = infer_format(arg, fieldmask, flds)
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(fmt, flds) = infer_format(arg, fieldmask, flds, width)
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arg = fmt.base
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for f in flds.keys():
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if f not in arg.fields:
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@ -687,7 +703,7 @@ def parse_generic(lineno, is_format, name, toks):
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if f not in flds.keys() and f not in fmt.fields.keys():
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error(lineno, 'field {0} not initialized'.format(f))
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pat = Pattern(name, lineno, fmt, fixedbits, fixedmask,
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undefmask, fieldmask, flds)
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undefmask, fieldmask, flds, width)
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patterns.append(pat)
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allpatterns.append(pat)
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@ -727,6 +743,13 @@ def build_multi_pattern(lineno, pats):
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if p.lineno < lineno:
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lineno = p.lineno
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width = None
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for p in pats:
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if width is None:
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width = p.width
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elif width != p.width:
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error(lineno, 'width mismatch in patterns within braces')
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repeat = True
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while repeat:
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if fixedmask == 0:
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@ -742,7 +765,7 @@ def build_multi_pattern(lineno, pats):
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else:
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repeat = False
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mp = MultiPattern(lineno, pats, fixedbits, fixedmask, undefmask)
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mp = MultiPattern(lineno, pats, fixedbits, fixedmask, undefmask, width)
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patterns.append(mp)
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# end build_multi_pattern
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@ -872,7 +895,7 @@ class Tree:
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# extract the fields now.
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if not extracted and self.base:
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output(ind, self.base.extract_name(),
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'(&u.f_', self.base.base.name, ', insn);\n')
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'(ctx, &u.f_', self.base.base.name, ', insn);\n')
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extracted = True
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# Attempt to aid the compiler in producing compact switch statements.
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@ -943,6 +966,147 @@ def build_tree(pats, outerbits, outermask):
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# end build_tree
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class SizeTree:
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"""Class representing a node in a size decode tree"""
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def __init__(self, m, w):
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self.mask = m
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self.subs = []
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self.base = None
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self.width = w
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def str1(self, i):
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ind = str_indent(i)
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r = '{0}{1:08x}'.format(ind, self.mask)
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r += ' [\n'
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for (b, s) in self.subs:
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r += '{0} {1:08x}:\n'.format(ind, b)
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r += s.str1(i + 4) + '\n'
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r += ind + ']'
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return r
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def __str__(self):
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return self.str1(0)
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def output_code(self, i, extracted, outerbits, outermask):
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ind = str_indent(i)
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# If we need to load more bytes to test, do so now.
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if extracted < self.width:
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output(ind, 'insn = ', decode_function,
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'_load_bytes(ctx, insn, {0}, {1});\n'
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.format(extracted / 8, self.width / 8));
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extracted = self.width
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# Attempt to aid the compiler in producing compact switch statements.
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# If the bits in the mask are contiguous, extract them.
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sh = is_contiguous(self.mask)
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if sh > 0:
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# Propagate SH down into the local functions.
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def str_switch(b, sh=sh):
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return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
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def str_case(b, sh=sh):
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return '0x{0:x}'.format(b >> sh)
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else:
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def str_switch(b):
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return 'insn & 0x{0:08x}'.format(b)
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def str_case(b):
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return '0x{0:08x}'.format(b)
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output(ind, 'switch (', str_switch(self.mask), ') {\n')
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for b, s in sorted(self.subs):
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innermask = outermask | self.mask
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innerbits = outerbits | b
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output(ind, 'case ', str_case(b), ':\n')
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output(ind, ' /* ',
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str_match_bits(innerbits, innermask), ' */\n')
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s.output_code(i + 4, extracted, innerbits, innermask)
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output(ind, '}\n')
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output(ind, 'return insn;\n')
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# end SizeTree
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class SizeLeaf:
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"""Class representing a leaf node in a size decode tree"""
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def __init__(self, m, w):
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self.mask = m
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self.width = w
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def str1(self, i):
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ind = str_indent(i)
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return '{0}{1:08x}'.format(ind, self.mask)
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def __str__(self):
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return self.str1(0)
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def output_code(self, i, extracted, outerbits, outermask):
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global decode_function
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ind = str_indent(i)
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# If we need to load more bytes, do so now.
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if extracted < self.width:
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output(ind, 'insn = ', decode_function,
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'_load_bytes(ctx, insn, {0}, {1});\n'
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.format(extracted / 8, self.width / 8));
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extracted = self.width
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output(ind, 'return insn;\n')
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# end SizeLeaf
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def build_size_tree(pats, width, outerbits, outermask):
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global insnwidth
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# Collect the mask of bits that are fixed in this width
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innermask = 0xff << (insnwidth - width)
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innermask &= ~outermask
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minwidth = None
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onewidth = True
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for i in pats:
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innermask &= i.fixedmask
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if minwidth is None:
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minwidth = i.width
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elif minwidth != i.width:
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onewidth = False;
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if minwidth < i.width:
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minwidth = i.width
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if onewidth:
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return SizeLeaf(innermask, minwidth)
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if innermask == 0:
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if width < minwidth:
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return build_size_tree(pats, width + 8, outerbits, outermask)
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pnames = []
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for p in pats:
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pnames.append(p.name + ':' + p.file + ':' + str(p.lineno))
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error_with_file(pats[0].file, pats[0].lineno,
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'overlapping patterns size {0}:'.format(width), pnames)
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bins = {}
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for i in pats:
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fb = i.fixedbits & innermask
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if fb in bins:
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bins[fb].append(i)
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else:
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bins[fb] = [i]
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fullmask = outermask | innermask
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lens = sorted(bins.keys())
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if len(lens) == 1:
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b = lens[0]
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return build_size_tree(bins[b], width + 8, b | outerbits, fullmask)
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r = SizeTree(innermask, width)
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for b, l in bins.items():
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s = build_size_tree(l, width, b | outerbits, fullmask)
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r.subs.append((b, s))
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return r
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# end build_size_tree
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def prop_format(tree):
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"""Propagate Format objects into the decode tree"""
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@ -965,6 +1129,23 @@ def prop_format(tree):
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# end prop_format
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def prop_size(tree):
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"""Propagate minimum widths up the decode size tree"""
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if isinstance(tree, SizeTree):
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min = None
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for (b, s) in tree.subs:
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width = prop_size(s)
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if min is None or min > width:
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min = width
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assert min >= tree.width
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tree.width = min
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else:
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min = tree.width
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return min
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# end prop_size
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def main():
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global arguments
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global formats
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@ -979,13 +1160,14 @@ def main():
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global insntype
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global insnmask
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global decode_function
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global variablewidth
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decode_scope = 'static '
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long_opts = ['decode=', 'translate=', 'output=', 'insnwidth=',
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'static-decode=']
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'static-decode=', 'varinsnwidth=']
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try:
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(opts, args) = getopt.getopt(sys.argv[1:], 'o:w:', long_opts)
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(opts, args) = getopt.getopt(sys.argv[1:], 'o:vw:', long_opts)
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except getopt.GetoptError as err:
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error(0, err)
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for o, a in opts:
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@ -999,7 +1181,9 @@ def main():
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elif o == '--translate':
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translate_prefix = a
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translate_scope = ''
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elif o in ('-w', '--insnwidth'):
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elif o in ('-w', '--insnwidth', '--varinsnwidth'):
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if o == '--varinsnwidth':
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variablewidth = True
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insnwidth = int(a)
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if insnwidth == 16:
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insntype = 'uint16_t'
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@ -1017,8 +1201,12 @@ def main():
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parse_file(f)
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f.close()
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t = build_tree(patterns, 0, 0)
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prop_format(t)
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if variablewidth:
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stree = build_size_tree(patterns, 8, 0, 0)
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prop_size(stree)
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dtree = build_tree(patterns, 0, 0)
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prop_format(dtree)
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if output_file:
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output_fd = open(output_file, 'w')
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@ -1059,11 +1247,18 @@ def main():
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f = arguments[n]
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output(i4, i4, f.struct_name(), ' f_', f.name, ';\n')
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output(i4, '} u;\n\n')
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t.output_code(4, False, 0, 0)
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dtree.output_code(4, False, 0, 0)
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output(i4, 'return false;\n')
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output('}\n')
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if variablewidth:
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output('\n', decode_scope, insntype, ' ', decode_function,
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'_load(DisasContext *ctx)\n{\n',
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' ', insntype, ' insn = 0;\n\n')
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stree.output_code(4, 0, 0, 0)
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output('}\n')
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if output_file:
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output_fd.close()
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# end main
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@ -54,35 +54,35 @@ typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv_ptr, TCGv_ptr,
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/* See e.g. ASR (immediate, predicated).
|
||||
* Returns -1 for unallocated encoding; diagnose later.
|
||||
*/
|
||||
static int tszimm_esz(int x)
|
||||
static int tszimm_esz(DisasContext *s, int x)
|
||||
{
|
||||
x >>= 3; /* discard imm3 */
|
||||
return 31 - clz32(x);
|
||||
}
|
||||
|
||||
static int tszimm_shr(int x)
|
||||
static int tszimm_shr(DisasContext *s, int x)
|
||||
{
|
||||
return (16 << tszimm_esz(x)) - x;
|
||||
return (16 << tszimm_esz(s, x)) - x;
|
||||
}
|
||||
|
||||
/* See e.g. LSL (immediate, predicated). */
|
||||
static int tszimm_shl(int x)
|
||||
static int tszimm_shl(DisasContext *s, int x)
|
||||
{
|
||||
return x - (8 << tszimm_esz(x));
|
||||
return x - (8 << tszimm_esz(s, x));
|
||||
}
|
||||
|
||||
static inline int plus1(int x)
|
||||
static inline int plus1(DisasContext *s, int x)
|
||||
{
|
||||
return x + 1;
|
||||
}
|
||||
|
||||
/* The SH bit is in bit 8. Extract the low 8 and shift. */
|
||||
static inline int expand_imm_sh8s(int x)
|
||||
static inline int expand_imm_sh8s(DisasContext *s, int x)
|
||||
{
|
||||
return (int8_t)x << (x & 0x100 ? 8 : 0);
|
||||
}
|
||||
|
||||
static inline int expand_imm_sh8u(int x)
|
||||
static inline int expand_imm_sh8u(DisasContext *s, int x)
|
||||
{
|
||||
return (uint8_t)x << (x & 0x100 ? 8 : 0);
|
||||
}
|
||||
@ -90,7 +90,7 @@ static inline int expand_imm_sh8u(int x)
|
||||
/* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype)
|
||||
* with unsigned data. C.f. SVE Memory Contiguous Load Group.
|
||||
*/
|
||||
static inline int msz_dtype(int msz)
|
||||
static inline int msz_dtype(DisasContext *s, int msz)
|
||||
{
|
||||
static const uint8_t dtype[4] = { 0, 5, 10, 15 };
|
||||
return dtype[msz];
|
||||
@ -4834,7 +4834,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
|
||||
int desc, poff;
|
||||
|
||||
/* Load the first quadword using the normal predicated load helpers. */
|
||||
desc = sve_memopidx(s, msz_dtype(msz));
|
||||
desc = sve_memopidx(s, msz_dtype(s, msz));
|
||||
desc |= zt << MEMOPIDX_SHIFT;
|
||||
desc = simd_desc(16, 16, desc);
|
||||
t_desc = tcg_const_i32(desc);
|
||||
@ -5016,7 +5016,7 @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
|
||||
fn = fn_multiple[be][nreg - 1][msz];
|
||||
}
|
||||
assert(fn != NULL);
|
||||
do_mem_zpa(s, zt, pg, addr, msz_dtype(msz), fn);
|
||||
do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), fn);
|
||||
}
|
||||
|
||||
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
|
||||
@ -5065,7 +5065,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
|
||||
TCGv_i32 t_desc;
|
||||
int desc;
|
||||
|
||||
desc = sve_memopidx(s, msz_dtype(msz));
|
||||
desc = sve_memopidx(s, msz_dtype(s, msz));
|
||||
desc |= scale << MEMOPIDX_SHIFT;
|
||||
desc = simd_desc(vsz, vsz, desc);
|
||||
t_desc = tcg_const_i32(desc);
|
||||
|
||||
@ -279,7 +279,7 @@ typedef struct DisasContext {
|
||||
} DisasContext;
|
||||
|
||||
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
|
||||
static int expand_sm_imm(int val)
|
||||
static int expand_sm_imm(DisasContext *ctx, int val)
|
||||
{
|
||||
if (val & PSW_SM_E) {
|
||||
val = (val & ~PSW_SM_E) | PSW_E;
|
||||
@ -291,43 +291,43 @@ static int expand_sm_imm(int val)
|
||||
}
|
||||
|
||||
/* Inverted space register indicates 0 means sr0 not inferred from base. */
|
||||
static int expand_sr3x(int val)
|
||||
static int expand_sr3x(DisasContext *ctx, int val)
|
||||
{
|
||||
return ~val;
|
||||
}
|
||||
|
||||
/* Convert the M:A bits within a memory insn to the tri-state value
|
||||
we use for the final M. */
|
||||
static int ma_to_m(int val)
|
||||
static int ma_to_m(DisasContext *ctx, int val)
|
||||
{
|
||||
return val & 2 ? (val & 1 ? -1 : 1) : 0;
|
||||
}
|
||||
|
||||
/* Convert the sign of the displacement to a pre or post-modify. */
|
||||
static int pos_to_m(int val)
|
||||
static int pos_to_m(DisasContext *ctx, int val)
|
||||
{
|
||||
return val ? 1 : -1;
|
||||
}
|
||||
|
||||
static int neg_to_m(int val)
|
||||
static int neg_to_m(DisasContext *ctx, int val)
|
||||
{
|
||||
return val ? -1 : 1;
|
||||
}
|
||||
|
||||
/* Used for branch targets and fp memory ops. */
|
||||
static int expand_shl2(int val)
|
||||
static int expand_shl2(DisasContext *ctx, int val)
|
||||
{
|
||||
return val << 2;
|
||||
}
|
||||
|
||||
/* Used for fp memory ops. */
|
||||
static int expand_shl3(int val)
|
||||
static int expand_shl3(DisasContext *ctx, int val)
|
||||
{
|
||||
return val << 3;
|
||||
}
|
||||
|
||||
/* Used for assemble_21. */
|
||||
static int expand_shl11(int val)
|
||||
static int expand_shl11(DisasContext *ctx, int val)
|
||||
{
|
||||
return val << 11;
|
||||
}
|
||||
|
||||
@ -48,13 +48,13 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
|
||||
REQUIRE_EXT(ctx, RVF);
|
||||
|
||||
arg_c_lw tmp;
|
||||
decode_insn16_extract_cl_w(&tmp, ctx->opcode);
|
||||
decode_insn16_extract_cl_w(ctx, &tmp, ctx->opcode);
|
||||
arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
|
||||
return trans_flw(ctx, &arg);
|
||||
#else
|
||||
/* C.LD ( RV64C/RV128C-only ) */
|
||||
arg_c_fld tmp;
|
||||
decode_insn16_extract_cl_d(&tmp, ctx->opcode);
|
||||
decode_insn16_extract_cl_d(ctx, &tmp, ctx->opcode);
|
||||
arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
|
||||
return trans_ld(ctx, &arg);
|
||||
#endif
|
||||
@ -80,13 +80,13 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
|
||||
REQUIRE_EXT(ctx, RVF);
|
||||
|
||||
arg_c_sw tmp;
|
||||
decode_insn16_extract_cs_w(&tmp, ctx->opcode);
|
||||
decode_insn16_extract_cs_w(ctx, &tmp, ctx->opcode);
|
||||
arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
|
||||
return trans_fsw(ctx, &arg);
|
||||
#else
|
||||
/* C.SD ( RV64C/RV128C-only ) */
|
||||
arg_c_fsd tmp;
|
||||
decode_insn16_extract_cs_d(&tmp, ctx->opcode);
|
||||
decode_insn16_extract_cs_d(ctx, &tmp, ctx->opcode);
|
||||
arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
|
||||
return trans_sd(ctx, &arg);
|
||||
#endif
|
||||
@ -107,7 +107,7 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
|
||||
#ifdef TARGET_RISCV32
|
||||
/* C.JAL */
|
||||
arg_c_j tmp;
|
||||
decode_insn16_extract_cj(&tmp, ctx->opcode);
|
||||
decode_insn16_extract_cj(ctx, &tmp, ctx->opcode);
|
||||
arg_jal arg = { .rd = 1, .imm = tmp.imm };
|
||||
return trans_jal(ctx, &arg);
|
||||
#else
|
||||
|
||||
@ -517,7 +517,7 @@ static void decode_RV32_64C(DisasContext *ctx)
|
||||
}
|
||||
|
||||
#define EX_SH(amount) \
|
||||
static int ex_shift_##amount(int imm) \
|
||||
static int ex_shift_##amount(DisasContext *ctx, int imm) \
|
||||
{ \
|
||||
return imm << amount; \
|
||||
}
|
||||
@ -533,7 +533,7 @@ EX_SH(12)
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
static int ex_rvc_register(int reg)
|
||||
static int ex_rvc_register(DisasContext *ctx, int reg)
|
||||
{
|
||||
return 8 + reg;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user