mirror of https://gitlab.com/qemu-project/qemu
target/arm: Move vfp_expand_imm() to translate.[ch]
We want to use vfp_expand_imm() in the AArch32 VFP decode; move it from the a64-only header/source file to the AArch32 one (which is always compiled even for AArch64). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-2-peter.maydell@linaro.org
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@ -6380,38 +6380,6 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
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}
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}
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}
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}
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/* The imm8 encodes the sign bit, enough bits to represent an exponent in
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* the range 01....1xx to 10....0xx, and the most significant 4 bits of
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* the mantissa; see VFPExpandImm() in the v8 ARM ARM.
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*/
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uint64_t vfp_expand_imm(int size, uint8_t imm8)
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{
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uint64_t imm;
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switch (size) {
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case MO_64:
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
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extract32(imm8, 0, 6);
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imm <<= 48;
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break;
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case MO_32:
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
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(extract32(imm8, 0, 6) << 3);
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imm <<= 16;
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break;
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case MO_16:
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
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(extract32(imm8, 0, 6) << 6);
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break;
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default:
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g_assert_not_reached();
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}
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return imm;
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}
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/* Floating point immediate
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/* Floating point immediate
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* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
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* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
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* +---+---+---+-----------+------+---+------------+-------+------+------+
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* +---+---+---+-----------+------+---+------------+-------+------+------+
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@ -39,7 +39,6 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
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TCGv_ptr get_fpstatus_ptr(bool);
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TCGv_ptr get_fpstatus_ptr(bool);
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bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
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bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
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unsigned int imms, unsigned int immr);
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unsigned int imms, unsigned int immr);
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uint64_t vfp_expand_imm(int size, uint8_t imm8);
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bool sve_access_check(DisasContext *s);
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bool sve_access_check(DisasContext *s);
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/* We should have at some point before trying to access an FP register
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/* We should have at some point before trying to access an FP register
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@ -30,6 +30,39 @@
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#include "decode-vfp.inc.c"
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#include "decode-vfp.inc.c"
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#include "decode-vfp-uncond.inc.c"
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#include "decode-vfp-uncond.inc.c"
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/*
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* The imm8 encodes the sign bit, enough bits to represent an exponent in
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* the range 01....1xx to 10....0xx, and the most significant 4 bits of
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* the mantissa; see VFPExpandImm() in the v8 ARM ARM.
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*/
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uint64_t vfp_expand_imm(int size, uint8_t imm8)
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{
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uint64_t imm;
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switch (size) {
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case MO_64:
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
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extract32(imm8, 0, 6);
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imm <<= 48;
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break;
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case MO_32:
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
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(extract32(imm8, 0, 6) << 3);
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imm <<= 16;
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break;
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case MO_16:
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
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(extract32(imm8, 0, 6) << 6);
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break;
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default:
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g_assert_not_reached();
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}
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return imm;
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}
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/*
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/*
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* Return the offset of a 16-bit half of the specified VFP single-precision
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* Return the offset of a 16-bit half of the specified VFP single-precision
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* register. If top is true, returns the top 16 bits; otherwise the bottom
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* register. If top is true, returns the top 16 bits; otherwise the bottom
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@ -237,6 +237,13 @@ static inline void gen_ss_advance(DisasContext *s)
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}
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}
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}
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}
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/*
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* Given a VFP floating point constant encoded into an 8 bit immediate in an
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* instruction, expand it to the actual constant value of the specified
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* size, as per the VFPExpandImm() pseudocode in the Arm ARM.
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*/
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uint64_t vfp_expand_imm(int size, uint8_t imm8);
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/* Vector operations shared between ARM and AArch64. */
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/* Vector operations shared between ARM and AArch64. */
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extern const GVecGen3 mla_op[4];
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extern const GVecGen3 mla_op[4];
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extern const GVecGen3 mls_op[4];
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extern const GVecGen3 mls_op[4];
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