target/xtensa: Convert to 3-phase reset
Convert the xtensa CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20221124115023.2437291-20-peter.maydell@linaro.org
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@ -41,7 +41,7 @@ typedef struct XtensaConfig XtensaConfig;
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/**
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* XtensaCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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* @parent_phases: The parent class' reset phase handlers.
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* @config: The CPU core configuration.
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*
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* An Xtensa CPU model.
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@ -52,7 +52,7 @@ struct XtensaCPUClass {
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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ResettablePhases parent_phases;
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const XtensaConfig *config;
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};
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@ -85,16 +85,18 @@ bool xtensa_abi_call0(void)
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}
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#endif
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static void xtensa_cpu_reset(DeviceState *dev)
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static void xtensa_cpu_reset_hold(Object *obj)
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{
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CPUState *s = CPU(dev);
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CPUState *s = CPU(obj);
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XtensaCPU *cpu = XTENSA_CPU(s);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
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CPUXtensaState *env = &cpu->env;
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bool dfpu = xtensa_option_enabled(env->config,
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XTENSA_OPTION_DFP_COPROCESSOR);
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xcc->parent_reset(dev);
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if (xcc->parent_phases.hold) {
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xcc->parent_phases.hold(obj);
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}
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env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
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env->sregs[LITBASE] &= ~1;
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@ -240,11 +242,13 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
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ResettableClass *rc = RESETTABLE_CLASS(oc);
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device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
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&xcc->parent_realize);
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device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
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resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL,
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&xcc->parent_phases);
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cc->class_by_name = xtensa_cpu_class_by_name;
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cc->has_work = xtensa_cpu_has_work;
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