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hw/pci-bridge/pcie_pci_bridge: properly handle MSI unavailability case

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QEMU with the pcie-pci-bridge device crashes if the guest board doesn't support MSI,
e.g. 'qemu-system-ppc64 -M prep -device pcie-pci-bridge'.
This is caused by wrong pcie-pci-bridge instantiation error handling. This patch fixes this issue
by falling back to legacy INTx if MSI is not available.
Also set the bridge's 'msi' property default value to 'auto' in order to trigger errors
only when user explicitly set msi=on.

Reported-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Aleksandr Bezzubikov 2017-09-25 02:21:58 +03:00 committed by Michael S. Tsirkin
parent 9cd1e97a7a
commit d659d94013
1 changed files with 18 additions and 6 deletions
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24
hw/pci-bridge/pcie_pci_bridge.c
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@ -65,10 +65,18 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp)
goto aer_error; goto aer_error;
} }
Error *local_err = NULL;
if (pcie_br->msi != ON_OFF_AUTO_OFF) { if (pcie_br->msi != ON_OFF_AUTO_OFF) {
rc = msi_init(d, 0, 1, true, true, errp); rc = msi_init(d, 0, 1, true, true, &local_err);
if (rc < 0) { if (rc < 0) {
goto msi_error; assert(rc == -ENOTSUP);
if (pcie_br->msi != ON_OFF_AUTO_ON) {
error_free(local_err);
} else {
/* failed to satisfy user's explicit request for MSI */
error_propagate(errp, local_err);
goto msi_error;
}
} }
} }
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
@ -81,7 +89,7 @@ aer_error:
pm_error: pm_error:
pcie_cap_exit(d); pcie_cap_exit(d);
cap_error: cap_error:
shpc_free(d); shpc_cleanup(d, &pcie_br->shpc_bar);
error: error:
pci_bridge_exitfn(d); pci_bridge_exitfn(d);
} }
@ -98,7 +106,9 @@ static void pcie_pci_bridge_reset(DeviceState *qdev)
{ {
PCIDevice *d = PCI_DEVICE(qdev); PCIDevice *d = PCI_DEVICE(qdev);
pci_bridge_reset(qdev); pci_bridge_reset(qdev);
msi_reset(d); if (msi_present(d)) {
msi_reset(d);
}
shpc_reset(d); shpc_reset(d);
} }
@ -106,12 +116,14 @@ static void pcie_pci_bridge_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len) uint32_t address, uint32_t val, int len)
{ {
pci_bridge_write_config(d, address, val, len); pci_bridge_write_config(d, address, val, len);
msi_write_config(d, address, val, len); if (msi_present(d)) {
msi_write_config(d, address, val, len);
}
shpc_cap_write_config(d, address, val, len); shpc_cap_write_config(d, address, val, len);
} }
static Property pcie_pci_bridge_dev_properties[] = { static Property pcie_pci_bridge_dev_properties[] = {
DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUTO),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };