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target/ppc: Introduce an mmu_is_64bit() helper

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Callers don't really need to know how 64-bit MMU model enums are
computed. Hide this in a helper.

Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20201209173536.1437351-3-groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Greg Kurz 2020-12-09 18:35:36 +01:00 committed by David Gibson
parent d55dfd446c
commit d57d72a874
7 changed files with 17 additions and 12 deletions
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5
target/ppc/cpu-qom.h
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@ -74,6 +74,11 @@ enum powerpc_mmu_t {
POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
};
static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
{
return mmu_model & POWERPC_MMU_64;
}
/*****************************************************************************/
/* Exception model */
typedef enum powerpc_excp_t powerpc_excp_t;

4
target/ppc/excp_helper.c
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@ -266,7 +266,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
*/
if (excp == POWERPC_EXCP_HV_EMU
#if defined(TARGET_PPC64)
&& !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB))
&& !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
#endif /* defined(TARGET_PPC64) */
) {
@ -824,7 +824,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
vector = (uint32_t)vector;
}
} else {
if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
vector = (uint32_t)vector;
} else {
new_msr |= (target_ulong)1 << MSR_SF;

4
target/ppc/machine.c
View File

@ -550,7 +550,7 @@ static bool sr_needed(void *opaque)
#ifdef TARGET_PPC64
PowerPCCPU *cpu = opaque;
return !(cpu->env.mmu_model & POWERPC_MMU_64);
return !mmu_is_64bit(cpu->env.mmu_model);
#else
return true;
#endif
@ -606,7 +606,7 @@ static bool slb_needed(void *opaque)
PowerPCCPU *cpu = opaque;
/* We don't support any of the old segment table based 64-bit CPUs */
return cpu->env.mmu_model & POWERPC_MMU_64;
return mmu_is_64bit(cpu->env.mmu_model);
}
static int slb_post_load(void *opaque, int version_id)

2
target/ppc/mmu-hash64.c
View File

@ -1140,7 +1140,7 @@ void ppc_hash64_init(PowerPCCPU *cpu)
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
if (!pcc->hash64_opts) {
assert(!(env->mmu_model & POWERPC_MMU_64));
assert(!mmu_is_64bit(env->mmu_model));
return;
}

10
target/ppc/mmu_helper.c
View File

@ -2002,7 +2002,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
void ppc_tlb_invalidate_all(CPUPPCState *env)
{
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
if (mmu_is_64bit(env->mmu_model)) {
env->tlb_need_flush = 0;
tlb_flush(env_cpu(env));
} else
@ -2046,7 +2046,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
#if !defined(FLUSH_ALL_TLBS)
addr &= TARGET_PAGE_MASK;
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
if (mmu_is_64bit(env->mmu_model)) {
/* tlbie invalidate TLBs for all segments */
/*
* XXX: given the fact that there are too many segments to invalidate,
@ -2091,7 +2091,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
assert(!cpu->vhyp);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
if (mmu_is_64bit(env->mmu_model)) {
target_ulong sdr_mask = SDR_64_HTABORG | SDR_64_HTABSIZE;
target_ulong htabsize = value & SDR_64_HTABSIZE;
@ -2144,7 +2144,7 @@ void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
{
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
if (mmu_is_64bit(env->mmu_model)) {
/* XXX */
return 0;
}
@ -2158,7 +2158,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
"%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
(int)srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
if (mmu_is_64bit(env->mmu_model)) {
PowerPCCPU *cpu = env_archcpu(env);
uint64_t esid, vsid;

2
target/ppc/translate.c
View File

@ -7892,7 +7892,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->insns_flags = env->insns_flags;
ctx->insns_flags2 = env->insns_flags2;
ctx->access_type = -1;
ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64);
ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
ctx->flags = env->flags;

2
target/ppc/translate_init.c.inc
View File

@ -10671,7 +10671,7 @@ static void ppc_cpu_reset(DeviceState *dev)
#endif
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
if (mmu_is_64bit(env->mmu_model)) {
msr |= (1ULL << MSR_SF);
}
#endif