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hw/intc/arm_gic: Actually set the active bits for active interrupts

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Although we were correctly handling interrupts becoming active
and then inactive, we weren't actually exposing this to the guest
by setting the 'active' flag for the interrupt, so reads
of GICD_ICACTIVERn and GICD_ISACTIVERn would generally incorrectly
return zeroes. Correct this oversight.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1438089748-5528-6-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2015-09-08 17:38:43 +01:00
parent 72889c8a80
commit d5523a1365
1 changed files with 2 additions and 0 deletions
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2
hw/intc/arm_gic.c
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@ -262,6 +262,7 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
}
s->running_priority[cpu] = prio;
GIC_SET_ACTIVE(irq, 1 << cpu);
}
static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
@ -536,6 +537,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
*/
gic_drop_prio(s, cpu, group);
GIC_CLEAR_ACTIVE(irq, cm);
gic_update(s);
}