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Fix tcg/aarch64 buglet for Windows on ARM host (#947).

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Merge tag 'pull-tcg-20220331' of https://gitlab.com/rth7680/qemu into staging

Fix tcg/aarch64 buglet for Windows on ARM host (#947).

# gpg: Signature made Thu 31 Mar 2022 18:05:46 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20220331' of https://gitlab.com/rth7680/qemu:
  tcg/aarch64: Use 'ull' suffix to force 64-bit constant

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-03-31 18:36:08 +01:00
commit d5341e0913
1 changed files with 2 additions and 2 deletions
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4
tcg/aarch64/tcg-target.c.inc
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@ -1086,9 +1086,9 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
opc = I3405_MOVZ;
}
s0 = ctz64(t0) & (63 & -16);
t1 = t0 & ~(0xffffUL << s0);
t1 = t0 & ~(0xffffull << s0);
s1 = ctz64(t1) & (63 & -16);
t2 = t1 & ~(0xffffUL << s1);
t2 = t1 & ~(0xffffull << s1);
if (t2 == 0) {
tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0);
if (t1 != 0) {