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target/riscv: rvb: support and turn on B-extension from command line

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B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kito Cheng 2021-05-06 00:06:17 +08:00 committed by Alistair Francis
parent 3a4a43e4e2
commit d52e94081e
2 changed files with 5 additions and 0 deletions
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4
target/riscv/cpu.c
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@ -489,6 +489,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
if (cpu->cfg.ext_b) {
target_misa |= RVB;
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
@ -559,6 +562,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),

1
target/riscv/cpu.h
View File

@ -286,6 +286,7 @@ struct RISCVCPU {
bool ext_f;
bool ext_d;
bool ext_c;
bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;