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tcg/aarch64: Implement vector saturating arithmetic 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2018-12-18 07:14:23 +00:00
parent bc37faf4cb
commit d32648d445
2 changed files with 25 additions and 1 deletions
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2
tcg/aarch64/tcg-target.h
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@ -135,7 +135,7 @@ typedef enum {
#define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_DEFAULT_MO (0)

24
tcg/aarch64/tcg-target.inc.c
View File

@ -528,6 +528,10 @@ typedef enum {
I3616_CMHI = 0x2e203400, I3616_CMHI = 0x2e203400,
I3616_CMHS = 0x2e203c00, I3616_CMHS = 0x2e203c00,
I3616_CMEQ = 0x2e208c00, I3616_CMEQ = 0x2e208c00,
I3616_SQADD = 0x0e200c00,
I3616_SQSUB = 0x0e202c00,
I3616_UQADD = 0x2e200c00,
I3616_UQSUB = 0x2e202c00,
/* AdvSIMD two-reg misc. */ /* AdvSIMD two-reg misc. */
I3617_CMGT0 = 0x0e208800, I3617_CMGT0 = 0x0e208800,
@ -2137,6 +2141,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_orc_vec: case INDEX_op_orc_vec:
tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2); tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);
break; break;
case INDEX_op_ssadd_vec:
tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
break;
case INDEX_op_sssub_vec:
tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
break;
case INDEX_op_usadd_vec:
tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
break;
case INDEX_op_ussub_vec:
tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
break;
case INDEX_op_not_vec: case INDEX_op_not_vec:
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
break; break;
@ -2207,6 +2223,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shli_vec: case INDEX_op_shli_vec:
case INDEX_op_shri_vec: case INDEX_op_shri_vec:
case INDEX_op_sari_vec: case INDEX_op_sari_vec:
case INDEX_op_ssadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
return 1; return 1;
case INDEX_op_mul_vec: case INDEX_op_mul_vec:
return vece < MO_64; return vece < MO_64;
@ -2386,6 +2406,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_xor_vec: case INDEX_op_xor_vec:
case INDEX_op_andc_vec: case INDEX_op_andc_vec:
case INDEX_op_orc_vec: case INDEX_op_orc_vec:
case INDEX_op_ssadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
return &w_w_w; return &w_w_w;
case INDEX_op_not_vec: case INDEX_op_not_vec:
case INDEX_op_neg_vec: case INDEX_op_neg_vec: