prep: add PReP System I/O
This device is a partial duplicate of System I/O device available in hw/ppc/prep.c This new one doesn't have all the Motorola-specific registers. The old one should be deprecated and removed with the 'prep' machine. Partial documentation available at ftp://ftp.software.ibm.com/rs6000/technology/spec/srp1_1.exe section 6.1.5 (I/O Device Mapping) Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Hervé Poussineau
David Gibson
parent
3398b7428b
commit
d2f8415226
@ -16,6 +16,7 @@ obj-y += ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o
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obj-y += ppc4xx_pci.o
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# PReP
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obj-$(CONFIG_PREP) += prep.o
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obj-$(CONFIG_PREP) += prep_systemio.o
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# OldWorld PowerMac
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obj-$(CONFIG_MAC) += mac_oldworld.o
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# NewWorld PowerMac
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303
hw/ppc/prep_systemio.c
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303
hw/ppc/prep_systemio.c
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@ -0,0 +1,303 @@
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/*
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* QEMU PReP System I/O emulation
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*
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* Copyright (c) 2017 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/isa/isa.h"
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#include "exec/address-spaces.h"
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#include "qemu/error-report.h" /* for error_report() */
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#include "sysemu/sysemu.h" /* for vm_stop() */
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#include "cpu.h"
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#include "trace.h"
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#define TYPE_PREP_SYSTEMIO "prep-systemio"
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#define PREP_SYSTEMIO(obj) \
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OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO)
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/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
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#define PREP_BIT(n) (1 << (7 - (n)))
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typedef struct PrepSystemIoState {
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ISADevice parent_obj;
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MemoryRegion ppc_parity_mem;
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qemu_irq non_contiguous_io_map_irq;
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uint8_t sreset; /* 0x0092 */
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uint8_t equipment; /* 0x080c */
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uint8_t system_control; /* 0x081c */
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uint8_t iomap_type; /* 0x0850 */
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uint8_t ibm_planar_id; /* 0x0852 */
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qemu_irq softreset_irq;
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PortioList portio;
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} PrepSystemIoState;
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/* PORT 0092 -- Special Port 92 (Read/Write) */
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enum {
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PORT0092_SOFTRESET = PREP_BIT(7),
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PORT0092_LE_MODE = PREP_BIT(6),
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};
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static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val)
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{
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PrepSystemIoState *s = opaque;
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trace_prep_systemio_write(addr, val);
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s->sreset = val & PORT0092_SOFTRESET;
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qemu_set_irq(s->softreset_irq, s->sreset);
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if ((val & PORT0092_LE_MODE) != 0) {
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/* XXX Not supported yet */
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error_report("little-endian mode not supported");
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vm_stop(RUN_STATE_PAUSED);
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} else {
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/* Nothing to do */
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}
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}
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static uint32_t prep_port0092_read(void *opaque, uint32_t addr)
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{
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PrepSystemIoState *s = opaque;
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trace_prep_systemio_read(addr, s->sreset);
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return s->sreset;
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}
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/* PORT 0808 -- Hardfile Light Register (Write Only) */
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enum {
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PORT0808_HARDFILE_LIGHT_ON = PREP_BIT(7),
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};
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static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val)
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{
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trace_prep_systemio_write(addr, val);
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}
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/* PORT 0810 -- Password Protect 1 Register (Write Only) */
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/* reset by port 0x4D in the SIO */
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static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val)
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{
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trace_prep_systemio_write(addr, val);
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}
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/* PORT 0812 -- Password Protect 2 Register (Write Only) */
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/* reset by port 0x4D in the SIO */
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static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val)
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{
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trace_prep_systemio_write(addr, val);
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}
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/* PORT 0814 -- L2 Invalidate Register (Write Only) */
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static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val)
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{
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trace_prep_systemio_write(addr, val);
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}
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/* PORT 0818 -- Reserved for Keylock (Read Only) */
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enum {
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PORT0818_KEYLOCK_SIGNAL_HIGH = PREP_BIT(7),
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};
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static uint32_t prep_port0818_read(void *opaque, uint32_t addr)
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{
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uint32_t val = 0;
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trace_prep_systemio_read(addr, val);
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return val;
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}
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/* PORT 080C -- Equipment */
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enum {
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PORT080C_SCSIFUSE = PREP_BIT(1),
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PORT080C_L2_COPYBACK = PREP_BIT(4),
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PORT080C_L2_256 = PREP_BIT(5),
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PORT080C_UPGRADE_CPU = PREP_BIT(6),
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PORT080C_L2 = PREP_BIT(7),
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};
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static uint32_t prep_port080c_read(void *opaque, uint32_t addr)
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{
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PrepSystemIoState *s = opaque;
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trace_prep_systemio_read(addr, s->equipment);
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return s->equipment;
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}
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/* PORT 081C -- System Control Register (Read/Write) */
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enum {
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PORT081C_FLOPPY_MOTOR_INHIBIT = PREP_BIT(3),
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PORT081C_MASK_TEA = PREP_BIT(2),
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PORT081C_L2_UPDATE_INHIBIT = PREP_BIT(1),
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PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0),
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};
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static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val)
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{
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static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT |
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PORT081C_MASK_TEA |
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PORT081C_L2_UPDATE_INHIBIT |
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PORT081C_L2_CACHEMISS_INHIBIT;
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PrepSystemIoState *s = opaque;
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trace_prep_systemio_write(addr, val);
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s->system_control = val & mask;
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}
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static uint32_t prep_port081c_read(void *opaque, uint32_t addr)
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{
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PrepSystemIoState *s = opaque;
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trace_prep_systemio_read(addr, s->system_control);
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return s->system_control;
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}
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/* System Board Identification */
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static uint32_t prep_port0852_read(void *opaque, uint32_t addr)
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{
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PrepSystemIoState *s = opaque;
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trace_prep_systemio_read(addr, s->ibm_planar_id);
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return s->ibm_planar_id;
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}
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/* PORT 0850 -- I/O Map Type Register (Read/Write) */
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enum {
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PORT0850_IOMAP_NONCONTIGUOUS = PREP_BIT(7),
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};
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static uint32_t prep_port0850_read(void *opaque, uint32_t addr)
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{
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PrepSystemIoState *s = opaque;
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trace_prep_systemio_read(addr, s->iomap_type);
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return s->iomap_type;
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}
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static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val)
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{
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PrepSystemIoState *s = opaque;
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trace_prep_systemio_write(addr, val);
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qemu_set_irq(s->non_contiguous_io_map_irq,
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val & PORT0850_IOMAP_NONCONTIGUOUS);
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s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS;
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}
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static const MemoryRegionPortio ppc_io800_port_list[] = {
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{ 0x092, 1, 1, .read = prep_port0092_read,
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.write = prep_port0092_write, },
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{ 0x808, 1, 1, .write = prep_port0808_write, },
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{ 0x80c, 1, 1, .read = prep_port080c_read, },
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{ 0x810, 1, 1, .write = prep_port0810_write, },
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{ 0x812, 1, 1, .write = prep_port0812_write, },
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{ 0x814, 1, 1, .write = prep_port0814_write, },
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{ 0x818, 1, 1, .read = prep_port0818_read },
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{ 0x81c, 1, 1, .read = prep_port081c_read,
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.write = prep_port081c_write, },
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{ 0x850, 1, 1, .read = prep_port0850_read,
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.write = prep_port0850_write, },
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{ 0x852, 1, 1, .read = prep_port0852_read, },
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PORTIO_END_OF_LIST()
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};
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static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr,
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unsigned int size)
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{
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uint32_t val = 0;
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trace_prep_systemio_read((unsigned int)addr, val);
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return val;
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}
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static const MemoryRegionOps ppc_parity_error_ops = {
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.read = ppc_parity_error_readl,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void prep_systemio_realize(DeviceState *dev, Error **errp)
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{
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ISADevice *isa = ISA_DEVICE(dev);
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PrepSystemIoState *s = PREP_SYSTEMIO(dev);
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PowerPCCPU *cpu;
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qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1);
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s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS;
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qemu_set_irq(s->non_contiguous_io_map_irq,
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s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS);
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cpu = POWERPC_CPU(first_cpu);
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s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
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isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s,
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"systemio800");
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memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev),
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&ppc_parity_error_ops, s, "ppc-parity", 0x4);
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memory_region_add_subregion(get_system_memory(), 0xbfffeff0,
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&s->ppc_parity_mem);
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}
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static const VMStateDescription vmstate_prep_systemio = {
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.name = "prep_systemio",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(sreset, PrepSystemIoState),
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VMSTATE_UINT8(system_control, PrepSystemIoState),
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VMSTATE_UINT8(iomap_type, PrepSystemIoState),
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VMSTATE_END_OF_LIST()
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},
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};
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static Property prep_systemio_properties[] = {
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DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0),
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DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void prep_systemio_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = prep_systemio_realize;
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dc->vmsd = &vmstate_prep_systemio;
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dc->props = prep_systemio_properties;
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}
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static TypeInfo prep_systemio800_info = {
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.name = TYPE_PREP_SYSTEMIO,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(PrepSystemIoState),
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.class_init = prep_systemio_class_initfn,
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};
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static void prep_systemio_register_types(void)
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{
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type_register_static(&prep_systemio800_info);
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}
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type_init(prep_systemio_register_types)
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@ -74,3 +74,7 @@ ppc_tb_adjust(uint64_t offs1, uint64_t offs2, int64_t diff, int64_t seconds) "ad
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# hw/ppc/prep.c
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prep_io_800_writeb(uint32_t addr, uint32_t val) "0x%08" PRIx32 " => 0x%02" PRIx32
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prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRIx32
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# hw/ppc/prep_systemio.c
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prep_systemio_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
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prep_systemio_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
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