aspeed: Refactor UART init for multi-SoC machines
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also allow multi-SoC
boards to completely change the wiring of serial devices from the
command line to specific SoC UART's.
This also removes the uart-default property from the SoC, since the SoC
doesn't need to know what UART is the "default" on the machine anymore.
I tested this using the images and commands from the previous
refactoring, and another test image for the ast1030:
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
Fuji uses UART1:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
ast2600-evb uses uart-default=UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
Wedge100 uses UART3:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
AST1030 EVB uses UART5:
qemu-system-arm -machine ast1030-evb \
-kernel Y35BCL.elf -nographic
Fixes: 6827ff20b2
("hw: aspeed: Init all UART's with serial devices")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-4-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
parent
72a7c47393
commit
d2b3eaefb4
@ -26,6 +26,7 @@
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#include "qemu/error-report.h"
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#include "qemu/units.h"
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#include "hw/qdev-clock.h"
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#include "sysemu/sysemu.h"
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static struct arm_boot_info aspeed_board_binfo = {
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.board_id = -1, /* device-tree-only board */
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@ -301,6 +302,21 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
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&error_fatal);
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}
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static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
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{
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AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
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AspeedSoCState *s = &bmc->soc;
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
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for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
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if (uart == amc->uart_default) {
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continue;
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}
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aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
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}
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}
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static void aspeed_machine_init(MachineState *machine)
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{
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AspeedMachineState *bmc = ASPEED_MACHINE(machine);
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@ -346,8 +362,7 @@ static void aspeed_machine_init(MachineState *machine)
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object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
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ASPEED_SCU_PROT_KEY, &error_abort);
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}
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qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
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amc->uart_default);
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connect_serial_hds_to_uarts(bmc);
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qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
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aspeed_board_init_flashes(&bmc->soc.fmc,
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@ -1383,8 +1398,7 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
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object_property_set_link(OBJECT(&bmc->soc), "memory",
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OBJECT(get_system_memory()), &error_abort);
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qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
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amc->uart_default);
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connect_serial_hds_to_uarts(bmc);
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qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
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aspeed_board_init_flashes(&bmc->soc.fmc,
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@ -144,6 +144,10 @@ static void aspeed_soc_ast1030_init(Object *obj)
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object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
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}
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for (i = 0; i < sc->uarts_num; i++) {
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object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
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}
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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object_initialize_child(obj, "gpio", &s->gpio, typename);
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@ -255,7 +259,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
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sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
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/* UART */
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aspeed_soc_uart_init(s);
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if (!aspeed_soc_uart_realize(s, errp)) {
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return;
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}
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/* Timer */
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object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
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@ -214,6 +214,10 @@ static void aspeed_soc_ast2600_init(Object *obj)
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object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
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}
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for (i = 0; i < sc->uarts_num; i++) {
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object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
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}
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snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
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object_initialize_child(obj, "xdma", &s->xdma, typename);
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@ -386,7 +390,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
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/* UART */
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aspeed_soc_uart_init(s);
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if (!aspeed_soc_uart_realize(s, errp)) {
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return;
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}
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/* I2C */
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object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
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@ -208,6 +208,10 @@ static void aspeed_soc_init(Object *obj)
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TYPE_FTGMAC100);
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}
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for (i = 0; i < sc->uarts_num; i++) {
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object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
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}
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snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
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object_initialize_child(obj, "xdma", &s->xdma, typename);
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@ -315,7 +319,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
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/* UART */
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aspeed_soc_uart_init(s);
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if (!aspeed_soc_uart_realize(s, errp)) {
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return;
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}
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/* I2C */
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object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
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@ -482,8 +488,6 @@ static Property aspeed_soc_properties[] = {
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MemoryRegion *),
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DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default,
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ASPEED_DEV_UART5),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -573,23 +577,37 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
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return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
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}
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void aspeed_soc_uart_init(AspeedSoCState *s)
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bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i, uart;
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SerialMM *smm;
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/* Attach an 8250 to the IO space as our UART */
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serial_mm_init(s->memory, sc->memmap[s->uart_default], 2,
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aspeed_soc_get_irq(s, s->uart_default), 38400,
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serial_hd(0), DEVICE_LITTLE_ENDIAN);
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for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
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if (uart == s->uart_default) {
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uart++;
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for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
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smm = &s->uart[i];
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/* Chardev property is set by the machine. */
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qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
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qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
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qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
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qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
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if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
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return false;
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}
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serial_mm_init(s->memory, sc->memmap[uart], 2,
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aspeed_soc_get_irq(s, uart), 38400,
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serial_hd(i), DEVICE_LITTLE_ENDIAN);
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sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
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aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
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}
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return true;
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}
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void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i = dev - ASPEED_DEV_UART1;
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g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
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qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
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}
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/*
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@ -36,12 +36,14 @@
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#include "hw/misc/aspeed_lpc.h"
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#include "hw/misc/unimp.h"
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#include "hw/misc/aspeed_peci.h"
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#include "hw/char/serial.h"
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#define ASPEED_SPIS_NUM 2
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#define ASPEED_EHCIS_NUM 2
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#define ASPEED_WDTS_NUM 4
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#define ASPEED_CPUS_NUM 2
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#define ASPEED_MACS_NUM 4
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#define ASPEED_UARTS_NUM 13
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struct AspeedSoCState {
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/*< private >*/
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@ -79,7 +81,7 @@ struct AspeedSoCState {
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AspeedSDHCIState emmc;
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AspeedLPCState lpc;
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AspeedPECIState peci;
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uint32_t uart_default;
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SerialMM uart[ASPEED_UARTS_NUM];
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Clock *sysclk;
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UnimplementedDeviceState iomem;
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UnimplementedDeviceState video;
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@ -175,7 +177,8 @@ enum {
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};
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qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
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void aspeed_soc_uart_init(AspeedSoCState *s);
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bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
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void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
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bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
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void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
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void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
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