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hw: allwinner-r40: Complete uart devices

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R40 has eight UARTs, support both 16450 and 16550 compatible modes.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
qianfan Zhao 2023-06-06 10:19:32 +01:00 committed by Peter Maydell
parent dc2a070d12
commit d1e409c583
2 changed files with 39 additions and 3 deletions
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34
hw/arm/allwinner-r40.c
View File

@ -45,6 +45,13 @@ const hwaddr allwinner_r40_memmap[] = {
[AW_R40_DEV_CCU] = 0x01c20000, [AW_R40_DEV_CCU] = 0x01c20000,
[AW_R40_DEV_PIT] = 0x01c20c00, [AW_R40_DEV_PIT] = 0x01c20c00,
[AW_R40_DEV_UART0] = 0x01c28000, [AW_R40_DEV_UART0] = 0x01c28000,
[AW_R40_DEV_UART1] = 0x01c28400,
[AW_R40_DEV_UART2] = 0x01c28800,
[AW_R40_DEV_UART3] = 0x01c28c00,
[AW_R40_DEV_UART4] = 0x01c29000,
[AW_R40_DEV_UART5] = 0x01c29400,
[AW_R40_DEV_UART6] = 0x01c29800,
[AW_R40_DEV_UART7] = 0x01c29c00,
[AW_R40_DEV_GIC_DIST] = 0x01c81000, [AW_R40_DEV_GIC_DIST] = 0x01c81000,
[AW_R40_DEV_GIC_CPU] = 0x01c82000, [AW_R40_DEV_GIC_CPU] = 0x01c82000,
[AW_R40_DEV_GIC_HYP] = 0x01c84000, [AW_R40_DEV_GIC_HYP] = 0x01c84000,
@ -157,6 +164,13 @@ enum {
/* Shared Processor Interrupts */ /* Shared Processor Interrupts */
enum { enum {
AW_R40_GIC_SPI_UART0 = 1, AW_R40_GIC_SPI_UART0 = 1,
AW_R40_GIC_SPI_UART1 = 2,
AW_R40_GIC_SPI_UART2 = 3,
AW_R40_GIC_SPI_UART3 = 4,
AW_R40_GIC_SPI_UART4 = 17,
AW_R40_GIC_SPI_UART5 = 18,
AW_R40_GIC_SPI_UART6 = 19,
AW_R40_GIC_SPI_UART7 = 20,
AW_R40_GIC_SPI_TIMER0 = 22, AW_R40_GIC_SPI_TIMER0 = 22,
AW_R40_GIC_SPI_TIMER1 = 23, AW_R40_GIC_SPI_TIMER1 = 23,
AW_R40_GIC_SPI_MMC0 = 32, AW_R40_GIC_SPI_MMC0 = 32,
@ -384,9 +398,23 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
} }
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
serial_mm_init(get_system_memory(), s->memmap[AW_R40_DEV_UART0], 2, for (int i = 0; i < AW_R40_NUM_UARTS; i++) {
qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_UART0), static const int uart_irqs[AW_R40_NUM_UARTS] = {
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); AW_R40_GIC_SPI_UART0,
AW_R40_GIC_SPI_UART1,
AW_R40_GIC_SPI_UART2,
AW_R40_GIC_SPI_UART3,
AW_R40_GIC_SPI_UART4,
AW_R40_GIC_SPI_UART5,
AW_R40_GIC_SPI_UART6,
AW_R40_GIC_SPI_UART7,
};
const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i];
serial_mm_init(get_system_memory(), addr, 2,
qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
}
/* Unimplemented devices */ /* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) { for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {

8
include/hw/arm/allwinner-r40.h
View File

@ -41,6 +41,13 @@ enum {
AW_R40_DEV_CCU, AW_R40_DEV_CCU,
AW_R40_DEV_PIT, AW_R40_DEV_PIT,
AW_R40_DEV_UART0, AW_R40_DEV_UART0,
AW_R40_DEV_UART1,
AW_R40_DEV_UART2,
AW_R40_DEV_UART3,
AW_R40_DEV_UART4,
AW_R40_DEV_UART5,
AW_R40_DEV_UART6,
AW_R40_DEV_UART7,
AW_R40_DEV_GIC_DIST, AW_R40_DEV_GIC_DIST,
AW_R40_DEV_GIC_CPU, AW_R40_DEV_GIC_CPU,
AW_R40_DEV_GIC_HYP, AW_R40_DEV_GIC_HYP,
@ -70,6 +77,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
* which are currently emulated by the R40 SoC code. * which are currently emulated by the R40 SoC code.
*/ */
#define AW_R40_NUM_MMCS 4 #define AW_R40_NUM_MMCS 4
#define AW_R40_NUM_UARTS 8
struct AwR40State { struct AwR40State {
/*< private >*/ /*< private >*/