tcg/arm: fix TLB access in qemu-ld/st ops
The TCG arm backend considers likely that the offset to the TLB entries does not exceed 12 bits for mem_index = 0. In practice this is not true for at least the MIPS target. The current patch fixes that by loading the bits 23-12 with a separate instruction, and using loads with address writeback, independently of the value of mem_idx. In total this allow a 24-bit offset, which is a lot more than needed. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -639,6 +639,22 @@ static inline void tcg_out_ld32_12(TCGContext *s, int cond,
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(rn << 16) | (rd << 12) | ((-im) & 0xfff));
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}
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/* Offset pre-increment with base writeback. */
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static inline void tcg_out_ld32_12wb(TCGContext *s, int cond,
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int rd, int rn, tcg_target_long im)
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{
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/* ldr with writeback and both register equals is UNPREDICTABLE */
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assert(rd != rn);
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if (im >= 0) {
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tcg_out32(s, (cond << 28) | 0x05b00000 |
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(rn << 16) | (rd << 12) | (im & 0xfff));
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} else {
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tcg_out32(s, (cond << 28) | 0x05300000 |
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(rn << 16) | (rd << 12) | ((-im) & 0xfff));
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}
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}
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static inline void tcg_out_st32_12(TCGContext *s, int cond,
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int rd, int rn, tcg_target_long im)
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{
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@ -1071,7 +1087,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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{
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int addr_reg, data_reg, data_reg2, bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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int mem_index, s_bits, tlb_offset;
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TCGReg argreg;
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# if TARGET_LONG_BITS == 64
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int addr_reg2;
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@ -1111,19 +1127,15 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
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TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
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/* In the
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* ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_read))]
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* below, the offset is likely to exceed 12 bits if mem_index != 0 and
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* not exceed otherwise, so use an
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* add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
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* before.
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*/
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if (mem_index)
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/* We assume that the offset is contained within 20 bits. */
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tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
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assert(tlb_offset & ~0xfffff == 0);
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if (tlb_offset > 0xfff) {
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
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(mem_index << (TLB_SHIFT & 1)) |
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((16 - (TLB_SHIFT >> 1)) << 8));
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
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offsetof(CPUArchState, tlb_table[0][0].addr_read));
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0xa00 | (tlb_offset >> 12));
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tlb_offset &= 0xfff;
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}
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tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
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TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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/* Check alignment. */
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@ -1131,15 +1143,14 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
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0, addr_reg, (1 << s_bits) - 1);
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# if TARGET_LONG_BITS == 64
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/* XXX: possibly we could use a block data load or writeback in
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* the first access. */
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
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offsetof(CPUArchState, tlb_table[0][0].addr_read) + 4);
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/* XXX: possibly we could use a block data load in the first access. */
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4);
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
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TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
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# endif
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
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offsetof(CPUArchState, tlb_table[0][0].addend));
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_read));
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switch (opc) {
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case 0:
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@ -1288,7 +1299,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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{
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int addr_reg, data_reg, data_reg2, bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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int mem_index, s_bits, tlb_offset;
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TCGReg argreg;
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# if TARGET_LONG_BITS == 64
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int addr_reg2;
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@ -1325,19 +1336,15 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
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TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
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/* In the
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* ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_write))]
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* below, the offset is likely to exceed 12 bits if mem_index != 0 and
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* not exceed otherwise, so use an
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* add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
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* before.
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*/
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if (mem_index)
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/* We assume that the offset is contained within 20 bits. */
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tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
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assert(tlb_offset & ~0xfffff == 0);
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if (tlb_offset > 0xfff) {
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
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(mem_index << (TLB_SHIFT & 1)) |
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((16 - (TLB_SHIFT >> 1)) << 8));
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
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offsetof(CPUArchState, tlb_table[0][0].addr_write));
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0xa00 | (tlb_offset >> 12));
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tlb_offset &= 0xfff;
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}
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tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
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TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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/* Check alignment. */
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@ -1345,15 +1352,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
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0, addr_reg, (1 << s_bits) - 1);
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# if TARGET_LONG_BITS == 64
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/* XXX: possibly we could use a block data load or writeback in
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* the first access. */
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
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offsetof(CPUArchState, tlb_table[0][0].addr_write) + 4);
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/* XXX: possibly we could use a block data load in the first access. */
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4);
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
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TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
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# endif
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
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offsetof(CPUArchState, tlb_table[0][0].addend));
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_write));
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switch (opc) {
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case 0:
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