mipsnet: convert to qdev
Move mipsnet_init() function to mipssim machine Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -8,9 +8,6 @@ PCIBus *gt64120_register(qemu_irq *pic);
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/* bonito.c */
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/* bonito.c */
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PCIBus *bonito_init(qemu_irq *pic);
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PCIBus *bonito_init(qemu_irq *pic);
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/* mipsnet.c */
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void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
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/* jazz_led.c */
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/* jazz_led.c */
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void jazz_led_init(target_phys_addr_t base);
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void jazz_led_init(target_phys_addr_t base);
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@ -35,6 +35,8 @@
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#include "mips-bios.h"
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#include "mips-bios.h"
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#include "loader.h"
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#include "loader.h"
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#include "elf.h"
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#include "elf.h"
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#include "sysbus.h"
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#include "exec-memory.h"
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static struct _loaderparams {
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static struct _loaderparams {
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int ram_size;
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int ram_size;
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@ -112,6 +114,22 @@ static void main_cpu_reset(void *opaque)
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}
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}
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}
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}
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static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "mipsnet");
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qdev_set_nic_properties(dev, nd);
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, irq);
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memory_region_add_subregion(get_system_io(),
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base,
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sysbus_mmio_get_region(s, 0));
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}
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static void
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static void
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mips_mipssim_init (ram_addr_t ram_size,
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mips_mipssim_init (ram_addr_t ram_size,
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const char *boot_device,
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const char *boot_device,
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88
hw/mipsnet.c
88
hw/mipsnet.c
@ -1,7 +1,6 @@
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#include "hw.h"
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#include "hw.h"
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#include "mips.h"
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#include "net.h"
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#include "net.h"
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#include "isa.h"
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#include "sysbus.h"
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//#define DEBUG_MIPSNET_SEND
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//#define DEBUG_MIPSNET_SEND
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//#define DEBUG_MIPSNET_RECEIVE
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//#define DEBUG_MIPSNET_RECEIVE
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@ -25,6 +24,8 @@
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#define MAX_ETH_FRAME_SIZE 1514
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#define MAX_ETH_FRAME_SIZE 1514
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typedef struct MIPSnetState {
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typedef struct MIPSnetState {
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SysBusDevice busdev;
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uint32_t busy;
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uint32_t busy;
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uint32_t rx_count;
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uint32_t rx_count;
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uint32_t rx_read;
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uint32_t rx_read;
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@ -33,7 +34,7 @@ typedef struct MIPSnetState {
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uint32_t intctl;
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uint32_t intctl;
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uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
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uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
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uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
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uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
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int io_base;
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MemoryRegion io;
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qemu_irq irq;
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qemu_irq irq;
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NICState *nic;
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NICState *nic;
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NICConf conf;
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NICConf conf;
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@ -103,7 +104,8 @@ static ssize_t mipsnet_receive(VLANClientState *nc, const uint8_t *buf, size_t s
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return size;
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return size;
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}
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}
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static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
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static uint64_t mipsnet_ioport_read(void *opaque, target_phys_addr_t addr,
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unsigned int size)
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{
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{
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MIPSnetState *s = opaque;
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MIPSnetState *s = opaque;
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int ret = 0;
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int ret = 0;
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@ -150,7 +152,8 @@ static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
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return ret;
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return ret;
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}
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}
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static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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static void mipsnet_ioport_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned int size)
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{
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{
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MIPSnetState *s = opaque;
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MIPSnetState *s = opaque;
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@ -224,11 +227,7 @@ static void mipsnet_cleanup(VLANClientState *nc)
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{
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{
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MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
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MIPSnetState *s = DO_UPCAST(NICState, nc, nc)->opaque;
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vmstate_unregister(NULL, &vmstate_mipsnet, s);
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s->nic = NULL;
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isa_unassign_ioport(s->io_base, 36);
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g_free(s);
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}
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}
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static NetClientInfo net_mipsnet_info = {
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static NetClientInfo net_mipsnet_info = {
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@ -239,35 +238,50 @@ static NetClientInfo net_mipsnet_info = {
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.cleanup = mipsnet_cleanup,
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.cleanup = mipsnet_cleanup,
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};
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};
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void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
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static MemoryRegionOps mipsnet_ioport_ops = {
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.read = mipsnet_ioport_read,
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.write = mipsnet_ioport_write,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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};
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static int mipsnet_sysbus_init(SysBusDevice *dev)
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{
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{
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MIPSnetState *s;
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MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev, dev);
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qemu_check_nic_model(nd, "mipsnet");
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memory_region_init_io(&s->io, &mipsnet_ioport_ops, s, "mipsnet-io", 36);
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sysbus_init_mmio_region(dev, &s->io);
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sysbus_init_irq(dev, &s->irq);
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s = g_malloc0(sizeof(MIPSnetState));
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s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
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dev->qdev.info->name, dev->qdev.id, s);
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qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
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register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
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return 0;
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register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
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register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
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register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
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register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
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register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
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s->io_base = base;
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s->irq = irq;
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if (nd) {
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s->conf.macaddr = nd->macaddr;
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s->conf.vlan = nd->vlan;
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s->conf.peer = nd->netdev;
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s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
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nd->model, nd->name, s);
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qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
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}
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mipsnet_reset(s);
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vmstate_register(NULL, 0, &vmstate_mipsnet, s);
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}
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}
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static void mipsnet_sysbus_reset(DeviceState *dev)
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{
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MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev.qdev, dev);
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mipsnet_reset(s);
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}
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static SysBusDeviceInfo mipsnet_info = {
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.init = mipsnet_sysbus_init,
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.qdev.name = "mipsnet",
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.qdev.desc = "MIPS Simulator network device",
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.qdev.size = sizeof(MIPSnetState),
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.qdev.vmsd = &vmstate_mipsnet,
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.qdev.reset = mipsnet_sysbus_reset,
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.qdev.props = (Property[]) {
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DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void mipsnet_register_devices(void)
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{
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sysbus_register_withprop(&mipsnet_info);
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}
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device_init(mipsnet_register_devices)
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