Add bus model (or input pins) into PowerPC CPU flags.
Add PowerPC 970 bus and exceptions model. Add code provision for PowerPC 970 instanciation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2680 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
08e46e54ea
commit
d0dfae6e91
122
hw/ppc.c
122
hw/ppc.c
@ -161,6 +161,128 @@ void ppc6xx_irq_init (CPUState *env)
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env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
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}
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/* PowerPC 970 internal IRQ controller */
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static void ppc970_set_irq (void *opaque, int pin, int level)
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{
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CPUState *env = opaque;
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int cur_level;
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
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env, pin, level);
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}
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#endif
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cur_level = (env->irq_input_state >> pin) & 1;
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/* Don't generate spurious events */
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if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
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switch (pin) {
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case PPC970_INPUT_INT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the external IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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break;
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case PPC970_INPUT_THINT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
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level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
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break;
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case PPC970_INPUT_MCP:
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/* Negative edge sensitive */
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/* XXX: TODO: actual reaction may depends on HID0 status
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* 603/604/740/750: check HID0[EMCP]
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*/
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if (cur_level == 1 && level == 0) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: raise machine check state\n",
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__func__);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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}
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break;
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case PPC970_INPUT_CKSTP:
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/* Level sensitive - active low */
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/* XXX: TODO: relay the signal to CKSTP_OUT pin */
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: stop the CPU\n", __func__);
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}
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#endif
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env->halted = 1;
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} else {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: restart the CPU\n", __func__);
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}
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#endif
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env->halted = 0;
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}
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break;
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case PPC970_INPUT_HRESET:
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/* Level sensitive - active low */
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if (level) {
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#if 0 // XXX: TOFIX
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: reset the CPU\n", __func__);
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}
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#endif
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cpu_reset(env);
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#endif
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}
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break;
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case PPC970_INPUT_SRESET:
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
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break;
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case PPC970_INPUT_TBEN:
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
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level);
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}
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#endif
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/* XXX: TODO */
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break;
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default:
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/* Unknown pin - do nothing */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
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}
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#endif
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return;
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}
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if (level)
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env->irq_input_state |= 1 << pin;
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else
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env->irq_input_state &= ~(1 << pin);
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}
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}
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void ppc970_irq_init (CPUState *env)
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{
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env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
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}
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/* PowerPC 405 internal IRQ controller */
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static void ppc405_set_irq (void *opaque, int pin, int level)
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{
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101
target-ppc/cpu.h
101
target-ppc/cpu.h
@ -393,7 +393,7 @@ enum {
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/* CPU run-time flags (MMU and exception model) */
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enum {
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/* MMU model */
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PPC_FLAGS_MMU_MASK = 0x0000000F,
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PPC_FLAGS_MMU_MASK = 0x000000FF,
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/* Standard 32 bits PowerPC MMU */
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PPC_FLAGS_MMU_32B = 0x00000000,
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/* Standard 64 bits PowerPC MMU */
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@ -406,38 +406,47 @@ enum {
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PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
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/* PowerPC 403 MMU */
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PPC_FLAGS_MMU_403 = 0x00000005,
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/* Freescale e500 MMU model */
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PPC_FLAGS_MMU_e500 = 0x00000006,
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/* BookE FSL MMU model */
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PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006,
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/* BookE MMU model */
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PPC_FLAGS_MMU_BOOKE = 0x00000007,
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/* 64 bits "bridge" PowerPC MMU */
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PPC_FLAGS_MMU_64BRIDGE = 0x00000008,
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/* Exception model */
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PPC_FLAGS_EXCP_MASK = 0x000000F0,
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PPC_FLAGS_EXCP_MASK = 0x0000FF00,
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/* Standard PowerPC exception model */
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PPC_FLAGS_EXCP_STD = 0x00000000,
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/* PowerPC 40x exception model */
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PPC_FLAGS_EXCP_40x = 0x00000010,
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PPC_FLAGS_EXCP_40x = 0x00000100,
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/* PowerPC 601 exception model */
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PPC_FLAGS_EXCP_601 = 0x00000020,
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PPC_FLAGS_EXCP_601 = 0x00000200,
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/* PowerPC 602 exception model */
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PPC_FLAGS_EXCP_602 = 0x00000030,
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PPC_FLAGS_EXCP_602 = 0x00000300,
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/* PowerPC 603 exception model */
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PPC_FLAGS_EXCP_603 = 0x00000040,
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PPC_FLAGS_EXCP_603 = 0x00000400,
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/* PowerPC 604 exception model */
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PPC_FLAGS_EXCP_604 = 0x00000050,
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PPC_FLAGS_EXCP_604 = 0x00000500,
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/* PowerPC 7x0 exception model */
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PPC_FLAGS_EXCP_7x0 = 0x00000060,
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PPC_FLAGS_EXCP_7x0 = 0x00000600,
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/* PowerPC 7x5 exception model */
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PPC_FLAGS_EXCP_7x5 = 0x00000070,
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PPC_FLAGS_EXCP_7x5 = 0x00000700,
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/* PowerPC 74xx exception model */
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PPC_FLAGS_EXCP_74xx = 0x00000080,
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PPC_FLAGS_EXCP_74xx = 0x00000800,
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/* PowerPC 970 exception model */
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PPC_FLAGS_EXCP_970 = 0x00000090,
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PPC_FLAGS_EXCP_970 = 0x00000900,
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/* BookE exception model */
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PPC_FLAGS_EXCP_BOOKE = 0x000000A0,
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PPC_FLAGS_EXCP_BOOKE = 0x00000A00,
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/* Input pins model */
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PPC_FLAGS_INPUT_MASK = 0x000F0000,
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PPC_FLAGS_INPUT_6xx = 0x00000000,
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PPC_FLAGS_INPUT_BookE = 0x00010000,
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PPC_FLAGS_INPUT_40x = 0x00020000,
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PPC_FLAGS_INPUT_970 = 0x00030000,
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};
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#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
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#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
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#define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK)
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/*****************************************************************************/
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/* Supported instruction set definitions */
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@ -454,64 +463,78 @@ enum {
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#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
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PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \
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PPC_40x_SPEC)
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#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
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#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \
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PPC_FLAGS_INPUT_40x)
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/* PowerPC 405 */
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#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
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PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \
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PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \
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PPC_405_MAC)
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#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
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#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
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PPC_FLAGS_INPUT_40x)
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/* PowerPC 440 */
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#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
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PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
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#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
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#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
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PPC_FLAGS_INPUT_BookE)
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/* Generic BookE PowerPC */
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#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
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PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
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#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
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#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
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PPC_FLAGS_INPUT_BookE)
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/* e500 core */
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#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
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PPC_CACHE_OPT | PPC_E500_VECTOR)
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#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
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#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
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PPC_FLAGS_INPUT_BookE)
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/* Non-embedded PowerPC */
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#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
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PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
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/* PowerPC 601 */
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#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
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#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
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#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \
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PPC_FLAGS_INPUT_6xx)
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/* PowerPC 602 */
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#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
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#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
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#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \
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PPC_FLAGS_INPUT_6xx)
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/* PowerPC 603 */
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#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
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#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
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#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
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PPC_FLAGS_INPUT_6xx)
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/* PowerPC G2 */
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#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
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#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
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#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
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PPC_FLAGS_INPUT_6xx)
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/* PowerPC 604 */
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#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
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PPC_MEM_TLBSYNC | PPC_TB)
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#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
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#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \
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PPC_FLAGS_INPUT_6xx)
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/* PowerPC 740/750 (aka G3) */
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#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
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PPC_MEM_TLBSYNC | PPC_TB)
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#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
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#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \
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PPC_FLAGS_INPUT_6xx)
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/* PowerPC 745/755 */
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#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
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PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
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#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
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#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \
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PPC_FLAGS_INPUT_6xx)
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/* PowerPC 74xx (aka G4) */
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#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
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PPC_MEM_TLBSYNC | PPC_TB)
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#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
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#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \
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PPC_FLAGS_INPUT_6xx)
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/* PowerPC 970 (aka G5) */
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#define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
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PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \
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PPC_64B | PPC_64_BRIDGE | PPC_SLBI)
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#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64B | PPC_FLAGS_EXCP_970)
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#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \
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PPC_FLAGS_INPUT_970)
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/* Default PowerPC will be 604/970 */
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#define PPC_INSNS_PPC32 PPC_INSNS_604
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@ -1347,6 +1370,17 @@ enum {
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PPC405_INPUT_DEBUG = 6,
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};
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enum {
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/* PowerPC 970 input pins */
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PPC970_INPUT_HRESET = 0,
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PPC970_INPUT_SRESET = 1,
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PPC970_INPUT_CKSTP = 2,
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PPC970_INPUT_TBEN = 3,
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PPC970_INPUT_MCP = 4,
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PPC970_INPUT_INT = 5,
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PPC970_INPUT_THINT = 6,
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};
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/* Hardware exceptions definitions */
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enum {
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/* External hardware exception sources */
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@ -1356,12 +1390,13 @@ enum {
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PPC_INTERRUPT_SMI = 3, /* System management interrupt */
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PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
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PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
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PPC_INTERRUPT_THERM = 6, /* Thermal exception */
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/* Internal hardware exception sources */
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PPC_INTERRUPT_DECR = 6, /* Decrementer exception */
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PPC_INTERRUPT_HDECR = 7, /* Hypervisor decrementer exception */
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PPC_INTERRUPT_PIT = 8, /* Programmable inteval timer interrupt */
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PPC_INTERRUPT_FIT = 9, /* Fixed interval timer interrupt */
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PPC_INTERRUPT_WDT = 10, /* Watchdog timer interrupt */
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PPC_INTERRUPT_DECR = 7, /* Decrementer exception */
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PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */
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PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */
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PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */
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PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */
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};
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/*****************************************************************************/
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@ -2003,6 +2003,13 @@ void ppc_hw_interrupt (CPUPPCState *env)
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env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
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#endif
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raised = 1;
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#if 0 // TODO
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/* Thermal interrupt */
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} else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
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env->exception_index = EXCP_970_THRM;
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env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
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raised = 1;
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#endif
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}
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#if 0 // TODO
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/* External debug exception */
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@ -48,6 +48,7 @@ void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
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#endif
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PPC_IRQ_INIT_FN(405);
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PPC_IRQ_INIT_FN(6xx);
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PPC_IRQ_INIT_FN(970);
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/* Generic callbacks:
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* do nothing but store/retrieve spr value
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@ -2350,6 +2351,8 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
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case CPU_PPC_POWER5: /* Power 5 */
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case CPU_PPC_POWER5P: /* Power 5+ */
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#endif
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break;
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case CPU_PPC_970: /* PowerPC 970 */
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case CPU_PPC_970FX10: /* PowerPC 970 FX */
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case CPU_PPC_970FX20:
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@ -2358,12 +2361,41 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
|
||||
case CPU_PPC_970FX31:
|
||||
case CPU_PPC_970MP10: /* PowerPC 970 MP */
|
||||
case CPU_PPC_970MP11:
|
||||
gen_spr_generic(env);
|
||||
gen_spr_ne_601(env);
|
||||
/* XXX: not correct */
|
||||
gen_low_BATs(env);
|
||||
/* Time base */
|
||||
gen_tbl(env);
|
||||
gen_spr_7xx(env);
|
||||
/* Hardware implementation registers */
|
||||
/* XXX : not implemented */
|
||||
spr_register(env, SPR_HID0, "HID0",
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
&spr_read_generic, &spr_write_generic,
|
||||
0x00000000);
|
||||
/* XXX : not implemented */
|
||||
spr_register(env, SPR_HID1, "HID1",
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
&spr_read_generic, &spr_write_generic,
|
||||
0x00000000);
|
||||
/* XXX : not implemented */
|
||||
spr_register(env, SPR_750_HID2, "HID2",
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
&spr_read_generic, &spr_write_generic,
|
||||
0x00000000);
|
||||
/* Allocate hardware IRQ controller */
|
||||
ppc970_irq_init(env);
|
||||
break;
|
||||
|
||||
#if defined (TODO)
|
||||
case CPU_PPC_CELL10: /* Cell family */
|
||||
case CPU_PPC_CELL20:
|
||||
case CPU_PPC_CELL30:
|
||||
case CPU_PPC_CELL31:
|
||||
#endif
|
||||
break;
|
||||
|
||||
#if defined (TODO)
|
||||
case CPU_PPC_RS64: /* Apache (RS64/A35) */
|
||||
case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */
|
||||
|
Loading…
Reference in New Issue
Block a user