tcx: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity
parent
fe06bd93e3
commit
d08151bf7c
152
hw/tcx.c
152
hw/tcx.c
@ -40,7 +40,15 @@ typedef struct TCXState {
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DisplayState *ds;
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uint8_t *vram;
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uint32_t *vram24, *cplane;
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ram_addr_t vram_offset, vram24_offset, cplane_offset;
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MemoryRegion vram_mem;
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MemoryRegion vram_8bit;
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MemoryRegion vram_24bit;
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MemoryRegion vram_cplane;
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MemoryRegion dac;
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MemoryRegion tec;
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MemoryRegion thc24;
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MemoryRegion thc8;
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ram_addr_t vram24_offset, cplane_offset;
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uint32_t vram_size;
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uint32_t palette[256];
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uint8_t r[256], g[256], b[256];
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@ -56,7 +64,7 @@ static void tcx_set_dirty(TCXState *s)
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unsigned int i;
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for (i = 0; i < MAXX * MAXY; i += TARGET_PAGE_SIZE) {
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cpu_physical_memory_set_dirty(s->vram_offset + i);
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memory_region_set_dirty(&s->vram_mem, i);
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}
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}
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@ -65,8 +73,8 @@ static void tcx24_set_dirty(TCXState *s)
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unsigned int i;
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for (i = 0; i < MAXX * MAXY * 4; i += TARGET_PAGE_SIZE) {
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cpu_physical_memory_set_dirty(s->vram24_offset + i);
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cpu_physical_memory_set_dirty(s->cplane_offset + i);
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memory_region_set_dirty(&s->vram_mem, s->vram24_offset + i);
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memory_region_set_dirty(&s->vram_mem, s->cplane_offset + i);
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}
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}
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@ -174,16 +182,18 @@ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
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}
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}
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static inline int check_dirty(ram_addr_t page, ram_addr_t page24,
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static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
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ram_addr_t cpage)
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{
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int ret;
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unsigned int off;
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ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
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ret = memory_region_get_dirty(&s->vram_mem, page, DIRTY_MEMORY_VGA);
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for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
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ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
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ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
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ret |= memory_region_get_dirty(&s->vram_mem, page24 + off,
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DIRTY_MEMORY_VGA);
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ret |= memory_region_get_dirty(&s->vram_mem, cpage + off,
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DIRTY_MEMORY_VGA);
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}
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return ret;
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}
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@ -192,16 +202,17 @@ static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
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ram_addr_t page_max, ram_addr_t page24,
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ram_addr_t cpage)
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{
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG);
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page_min -= ts->vram_offset;
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page_max -= ts->vram_offset;
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cpu_physical_memory_reset_dirty(page24 + page_min * 4,
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page24 + page_max * 4 + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG);
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cpu_physical_memory_reset_dirty(cpage + page_min * 4,
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cpage + page_max * 4 + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG);
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memory_region_reset_dirty(&ts->vram_mem,
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page_min, page_max + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA);
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memory_region_reset_dirty(&ts->vram_mem,
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page24 + page_min * 4,
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page24 + page_max * 4 + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA);
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memory_region_reset_dirty(&ts->vram_mem,
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cpage + page_min * 4,
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cpage + page_max * 4 + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA);
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}
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/* Fixed line length 1024 allows us to do nice tricks not possible on
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@ -216,7 +227,7 @@ static void tcx_update_display(void *opaque)
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if (ds_get_bits_per_pixel(ts->ds) == 0)
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return;
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page = ts->vram_offset;
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page = 0;
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y_start = -1;
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page_min = -1;
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page_max = 0;
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@ -242,7 +253,7 @@ static void tcx_update_display(void *opaque)
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}
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
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if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
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if (memory_region_get_dirty(&ts->vram_mem, page, DIRTY_MEMORY_VGA)) {
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if (y_start < 0)
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y_start = y;
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if (page < page_min)
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@ -279,8 +290,9 @@ static void tcx_update_display(void *opaque)
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}
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/* reset modified pages */
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if (page_max >= page_min) {
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG);
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memory_region_reset_dirty(&ts->vram_mem,
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page_min, page_max + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA);
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}
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}
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@ -294,7 +306,7 @@ static void tcx24_update_display(void *opaque)
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if (ds_get_bits_per_pixel(ts->ds) != 32)
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return;
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page = ts->vram_offset;
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page = 0;
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page24 = ts->vram24_offset;
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cpage = ts->cplane_offset;
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y_start = -1;
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@ -309,7 +321,7 @@ static void tcx24_update_display(void *opaque)
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
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page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
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if (check_dirty(page, page24, cpage)) {
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if (check_dirty(ts, page, page24, cpage)) {
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if (y_start < 0)
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y_start = y;
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if (page < page_min)
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@ -421,18 +433,20 @@ static void tcx_reset(DeviceState *d)
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s->r[255] = s->g[255] = s->b[255] = 255;
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update_palette_entries(s, 0, 256);
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memset(s->vram, 0, MAXX*MAXY);
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cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
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MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
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memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
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DIRTY_MEMORY_VGA);
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s->dac_index = 0;
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s->dac_state = 0;
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}
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static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
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static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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return 0;
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}
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static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
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unsigned size)
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{
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TCXState *s = opaque;
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@ -468,77 +482,77 @@ static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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return;
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}
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static CPUReadMemoryFunc * const tcx_dac_read[3] = {
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NULL,
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NULL,
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tcx_dac_readl,
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static const MemoryRegionOps tcx_dac_ops = {
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.read = tcx_dac_readl,
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.write = tcx_dac_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static CPUWriteMemoryFunc * const tcx_dac_write[3] = {
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NULL,
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NULL,
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tcx_dac_writel,
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};
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static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
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static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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return 0;
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}
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static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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static void dummy_writel(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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}
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static CPUReadMemoryFunc * const tcx_dummy_read[3] = {
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NULL,
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NULL,
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tcx_dummy_readl,
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};
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static CPUWriteMemoryFunc * const tcx_dummy_write[3] = {
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NULL,
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NULL,
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tcx_dummy_writel,
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static const MemoryRegionOps dummy_ops = {
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.read = dummy_readl,
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.write = dummy_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static int tcx_init1(SysBusDevice *dev)
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{
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TCXState *s = FROM_SYSBUS(TCXState, dev);
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int io_memory, dummy_memory;
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ram_addr_t vram_offset;
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ram_addr_t vram_offset = 0;
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int size;
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uint8_t *vram_base;
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vram_offset = qemu_ram_alloc(NULL, "tcx.vram", s->vram_size * (1 + 4 + 4));
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vram_base = qemu_get_ram_ptr(vram_offset);
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s->vram_offset = vram_offset;
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memory_region_init_ram(&s->vram_mem, NULL, "tcx.vram",
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s->vram_size * (1 + 4 + 4));
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vram_base = memory_region_get_ram_ptr(&s->vram_mem);
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/* 8-bit plane */
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s->vram = vram_base;
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size = s->vram_size;
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sysbus_init_mmio(dev, size, s->vram_offset);
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memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
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&s->vram_mem, vram_offset, size);
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sysbus_init_mmio_region(dev, &s->vram_8bit);
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vram_offset += size;
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vram_base += size;
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/* DAC */
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io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory);
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memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
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sysbus_init_mmio_region(dev, &s->dac);
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/* TEC (dummy) */
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dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write,
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s, DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory);
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memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
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sysbus_init_mmio_region(dev, &s->tec);
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/* THC: NetBSD writes here even with 8-bit display: dummy */
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sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory);
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memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
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TCX_THC_NREGS_24);
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sysbus_init_mmio_region(dev, &s->thc24);
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if (s->depth == 24) {
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/* 24-bit plane */
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size = s->vram_size * 4;
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s->vram24 = (uint32_t *)vram_base;
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s->vram24_offset = vram_offset;
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sysbus_init_mmio(dev, size, vram_offset);
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memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
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&s->vram_mem, vram_offset, size);
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sysbus_init_mmio_region(dev, &s->vram_24bit);
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vram_offset += size;
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vram_base += size;
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@ -546,14 +560,18 @@ static int tcx_init1(SysBusDevice *dev)
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size = s->vram_size * 4;
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s->cplane = (uint32_t *)vram_base;
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s->cplane_offset = vram_offset;
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sysbus_init_mmio(dev, size, vram_offset);
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memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
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&s->vram_mem, vram_offset, size);
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sysbus_init_mmio_region(dev, &s->vram_cplane);
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s->ds = graphic_console_init(tcx24_update_display,
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tcx24_invalidate_display,
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tcx24_screen_dump, NULL, s);
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} else {
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/* THC 8 bit (dummy) */
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sysbus_init_mmio(dev, TCX_THC_NREGS_8, dummy_memory);
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memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
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TCX_THC_NREGS_8);
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sysbus_init_mmio_region(dev, &s->thc8);
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s->ds = graphic_console_init(tcx_update_display,
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tcx_invalidate_display,
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