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Add register mappings in DSP space (must be accessible for MPU too).

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Don't set microwire CSR-busy bit too early.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3530 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2007-11-04 12:19:22 +00:00
parent 51a6527174
commit cf965d2406
4 changed files with 66 additions and 22 deletions
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76
hw/omap.c
View File

@ -1401,7 +1401,7 @@ struct omap_32khz_timer_s {
static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr - s->timer.base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* TVR */
@ -1424,7 +1424,7 @@ static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr - s->timer.base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* TVR */
@ -2894,7 +2894,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
switch (offset) {
@ -2950,7 +2950,7 @@ static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
@ -3142,7 +3142,7 @@ static void omap_gpio_set(void *opaque, int line, int level)
static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* DATA_INPUT */
@ -3172,7 +3172,7 @@ static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
@ -3322,7 +3322,7 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* RDR */
@ -3352,16 +3352,17 @@ static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* TDR */
s->txbuf = value; /* TD */
s->control |= 1 << 14; /* CSRB */
if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
(s->control & (1 << 12)))) /* CS_CMD */
(s->control & (1 << 12)))) { /* CS_CMD */
s->control |= 1 << 14; /* CSRB */
omap_uwire_transfer_start(s);
}
break;
case 0x04: /* CSR */
@ -3462,7 +3463,7 @@ void omap_pwl_update(struct omap_mpu_state_s *s)
static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr - s->pwl.base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* PWL_LEVEL */
@ -3478,7 +3479,7 @@ static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr - s->pwl.base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* PWL_LEVEL */
@ -3542,7 +3543,7 @@ static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr - s->pwt.base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* FRC */
@ -3560,7 +3561,7 @@ static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr - s->pwt.base;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* FRC */
@ -3679,7 +3680,7 @@ static inline int omap_rtc_bin(uint8_t num)
static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
uint8_t i;
switch (offset) {
@ -3757,7 +3758,7 @@ static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
struct tm new_tm;
time_t ti[2];
@ -4094,6 +4095,47 @@ static void omap_mpu_reset(void *opaque)
cpu_reset(mpu->env);
}
static const struct omap_map_s {
target_phys_addr_t phys_dsp;
target_phys_addr_t phys_mpu;
uint32_t size;
const char *name;
} omap15xx_dsp_mm[] = {
/* Strobe 0 */
{ 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
{ 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
{ 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
{ 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
{ 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
{ 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
{ 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
{ 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
{ 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
{ 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
{ 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
{ 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
{ 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
{ 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
{ 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
{ 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
{ 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
/* Strobe 1 */
{ 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
{ 0 }
};
static void omap_setup_dsp_mapping(const struct omap_map_s *map)
{
int io;
for (; map->phys_dsp; map ++) {
io = cpu_get_physical_page_desc(map->phys_mpu);
cpu_register_physical_memory(map->phys_dsp, map->size, io);
}
}
static void omap_mpu_wakeup(void *opaque, int irq, int req)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
@ -4241,6 +4283,8 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
* DSP MMU fffed200 - fffed2ff
*/
omap_setup_dsp_mapping(omap15xx_dsp_mm);
qemu_register_reset(omap_mpu_reset, s);
return s;

4
hw/omap.h
View File

@ -546,7 +546,6 @@ struct omap_mpu_state_s {
struct omap_uwire_s *microwire;
struct {
target_phys_addr_t base;
uint8_t output;
uint8_t level;
uint8_t enable;
@ -554,7 +553,6 @@ struct omap_mpu_state_s {
} pwl;
struct {
target_phys_addr_t base;
uint8_t frc;
uint8_t vrc;
uint8_t gcr;
@ -665,4 +663,6 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
# define OMAP_32B_REG(paddr)
# endif
# define OMAP_MPUI_REG_MASK 0x000007ff
#endif /* hw_omap_h */

4
hw/omap_i2c.c
View File

@ -194,7 +194,7 @@ void omap_i2c_reset(struct omap_i2c_s *s)
static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
switch (offset) {
@ -286,7 +286,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
int offset = addr - s->base;
int offset = addr & OMAP_MPUI_REG_MASK;
int nack;
switch (offset) {

4
hw/omap_mmc.c
View File

@ -269,7 +269,7 @@ static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
{
uint16_t i;
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
offset -= s->base;
offset &= OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* MMC_CMD */
@ -351,7 +351,7 @@ static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
{
int i;
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
offset -= s->base;
offset &= OMAP_MPUI_REG_MASK;
switch (offset) {
case 0x00: /* MMC_CMD */