apic: avoid passing CPUState from devices
Pass only APICState from pc.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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parent
9605111958
commit
cf6d64bfd9
32
hw/apic.c
32
hw/apic.c
@ -94,7 +94,7 @@
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#define MSI_ADDR_BASE 0xfee00000
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#define MSI_ADDR_SIZE 0x100000
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typedef struct APICState {
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struct APICState {
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CPUState *cpu_env;
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uint32_t apicbase;
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uint8_t id;
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@ -118,7 +118,7 @@ typedef struct APICState {
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QEMUTimer *timer;
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int sipi_vector;
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int wait_for_sipi;
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} APICState;
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};
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static int apic_io_memory;
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static APICState *local_apics[MAX_APICS + 1];
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@ -167,9 +167,8 @@ static inline int get_bit(uint32_t *tab, int index)
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return !!(tab[i] & mask);
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}
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static void apic_local_deliver(CPUState *env, int vector)
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static void apic_local_deliver(APICState *s, int vector)
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{
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APICState *s = env->apic_state;
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uint32_t lvt = s->lvt[vector];
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int trigger_mode;
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@ -180,15 +179,15 @@ static void apic_local_deliver(CPUState *env, int vector)
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switch ((lvt >> 8) & 7) {
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case APIC_DM_SMI:
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cpu_interrupt(env, CPU_INTERRUPT_SMI);
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
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break;
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case APIC_DM_NMI:
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cpu_interrupt(env, CPU_INTERRUPT_NMI);
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
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break;
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case APIC_DM_EXTINT:
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
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break;
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case APIC_DM_FIXED:
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@ -200,12 +199,11 @@ static void apic_local_deliver(CPUState *env, int vector)
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}
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}
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void apic_deliver_pic_intr(CPUState *env, int level)
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void apic_deliver_pic_intr(APICState *s, int level)
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{
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if (level)
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apic_local_deliver(env, APIC_LVT_LINT0);
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else {
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APICState *s = env->apic_state;
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0);
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} else {
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uint32_t lvt = s->lvt[APIC_LVT_LINT0];
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switch ((lvt >> 8) & 7) {
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@ -215,7 +213,7 @@ void apic_deliver_pic_intr(CPUState *env, int level)
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reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
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break;
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}
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}
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@ -591,9 +589,8 @@ static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
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trigger_mode);
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}
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int apic_get_interrupt(CPUState *env)
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int apic_get_interrupt(APICState *s)
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{
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APICState *s = env->apic_state;
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int intno;
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/* if the APIC is installed or enabled, we let the 8259 handle the
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@ -615,9 +612,8 @@ int apic_get_interrupt(CPUState *env)
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return intno;
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}
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int apic_accept_pic_intr(CPUState *env)
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int apic_accept_pic_intr(APICState *s)
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{
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APICState *s = env->apic_state;
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uint32_t lvt0;
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if (!s)
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@ -679,7 +675,7 @@ static void apic_timer(void *opaque)
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{
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APICState *s = opaque;
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apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
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apic_local_deliver(s, APIC_LVT_TIMER);
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apic_timer_update(s, s->next_time);
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}
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@ -1,14 +1,16 @@
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#ifndef APIC_H
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#define APIC_H
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/* apic.c */
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typedef struct APICState APICState;
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t trigger_mode);
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int apic_init(CPUState *env);
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int apic_accept_pic_intr(CPUState *env);
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void apic_deliver_pic_intr(CPUState *env, int level);
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int apic_get_interrupt(CPUState *env);
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int apic_accept_pic_intr(APICState *s);
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void apic_deliver_pic_intr(APICState *s, int level);
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int apic_get_interrupt(APICState *s);
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void apic_reset_irq_delivered(void);
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int apic_get_irq_delivered(void);
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10
hw/pc.c
10
hw/pc.c
@ -145,7 +145,7 @@ int cpu_get_pic_interrupt(CPUState *env)
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{
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int intno;
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intno = apic_get_interrupt(env);
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intno = apic_get_interrupt(env->apic_state);
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if (intno >= 0) {
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/* set irq request if a PIC irq is still pending */
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/* XXX: improve that */
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@ -153,8 +153,9 @@ int cpu_get_pic_interrupt(CPUState *env)
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return intno;
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}
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(env))
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if (!apic_accept_pic_intr(env->apic_state)) {
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return -1;
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}
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intno = pic_read_irq(isa_pic);
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return intno;
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@ -167,8 +168,9 @@ static void pic_irq_request(void *opaque, int irq, int level)
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DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
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if (env->apic_state) {
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while (env) {
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if (apic_accept_pic_intr(env))
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apic_deliver_pic_intr(env, level);
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if (apic_accept_pic_intr(env->apic_state)) {
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apic_deliver_pic_intr(env->apic_state, level);
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}
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env = env->next_cpu;
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}
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} else {
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