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target/riscv: Add zicfiss extension

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zicfiss [1] riscv cpu extension enables backward control flow integrity.

This patch sets up space for zicfiss extension in cpuconfig. And imple-
ments dependency on A, zicsr, zimop and zcmop extensions.

[1] - https://github.com/riscv/riscv-cfi

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-11-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Deepak Gupta 2024-10-08 15:50:00 -07:00 committed by Alistair Francis
parent ff81343e74
commit cf064a671a
3 changed files with 25 additions and 0 deletions
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1
target/riscv/cpu.c
View File

@ -107,6 +107,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp), ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp),
ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss),
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr),
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),

1
target/riscv/cpu_cfg.h
View File

@ -68,6 +68,7 @@ struct RISCVCPUConfig {
bool ext_zicbop; bool ext_zicbop;
bool ext_zicboz; bool ext_zicboz;
bool ext_zicfilp; bool ext_zicfilp;
bool ext_zicfiss;
bool ext_zicond; bool ext_zicond;
bool ext_zihintntl; bool ext_zihintntl;
bool ext_zihintpause; bool ext_zihintpause;

23
target/riscv/tcg/tcg-cpu.c
View File

@ -618,6 +618,29 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zihpm = false; cpu->cfg.ext_zihpm = false;
} }
if (cpu->cfg.ext_zicfiss) {
if (!cpu->cfg.ext_zicsr) {
error_setg(errp, "zicfiss extension requires zicsr extension");
return;
}
if (!riscv_has_ext(env, RVA)) {
error_setg(errp, "zicfiss extension requires A extension");
return;
}
if (!riscv_has_ext(env, RVS)) {
error_setg(errp, "zicfiss extension requires S");
return;
}
if (!cpu->cfg.ext_zimop) {
error_setg(errp, "zicfiss extension requires zimop extension");
return;
}
if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) {
error_setg(errp, "zicfiss with zca requires zcmop extension");
return;
}
}
if (!cpu->cfg.ext_zihpm) { if (!cpu->cfg.ext_zihpm) {
cpu->cfg.pmu_mask = 0; cpu->cfg.pmu_mask = 0;
cpu->pmu_avail_ctrs = 0; cpu->pmu_avail_ctrs = 0;