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target-cris: add v17 CPU

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In the CRIS v17 CPU an ADDC (add with carry) instruction has been added
compared to the v10 instruction set.

 Assembler syntax:

  ADDC [Rs],Rd
  ADDC [Rs+],Rd

 Size: Dword

 Description:

  The source data is added together with the carry flag to the
  destination register. The size of the operation is dword.

 Operation:

  Rd += s + C-flag;

 Flags affected:

  S R P U I X N Z V C
  - - - - - 0 * * * *

 Instruction format: ADDC [Rs],Rd

  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |Destination(Rd)| 1   0   0   1   1   0   1   0 |   Source(Rs)  |
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

 Instruction format: ADDC [Rs+],Rd

  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |Destination(Rd)| 1   1   0   1   1   0   1   0 |   Source(Rs)  |
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

[EI: Shorten 80+ lines]
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Rabin Vincent 2016-08-15 13:59:32 +02:00 committed by Edgar E. Iglesias
parent 17bc37b75e
commit ceffd34e85
3 changed files with 38 additions and 0 deletions
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14
target-cris/cpu.c
View File

@ -246,6 +246,16 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
}
static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 17;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
{
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
@ -272,6 +282,10 @@ static const TypeInfo cris_cpu_model_type_infos[] = {
.name = TYPE("crisv11"),
.parent = TYPE_CRIS_CPU,
.class_init = crisv11_cpu_class_init,
}, {
.name = TYPE("crisv17"),
.parent = TYPE_CRIS_CPU,
.class_init = crisv17_cpu_class_init,
}, {
.name = TYPE("crisv32"),
.parent = TYPE_CRIS_CPU,

1
target-cris/crisv10-decode.h
View File

@ -92,6 +92,7 @@
#define CRISV10_IND_JUMP_M 4
#define CRISV10_IND_DIP 5
#define CRISV10_IND_JUMP_R 6
#define CRISV17_IND_ADDC 6
#define CRISV10_IND_BOUND 7
#define CRISV10_IND_BCC_M 7
#define CRISV10_IND_MOVE_M_SPR 8

23
target-cris/translate_v10.c
View File

@ -1094,6 +1094,29 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
insn_len = dec10_bdap_m(env, dc, size);
break;
default:
/*
* ADDC for v17:
*
* Instruction format: ADDC [Rs],Rd
*
* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
* |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)|
* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
*
* Instruction format: ADDC [Rs+],Rd
*
* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
* |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)|
* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
*/
if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 &&
env->pregs[PR_VR] == 17) {
LOG_DIS("addc op=%d %d\n", dc->src, dc->dst);
cris_cc_mask(dc, CC_MASK_NZVC);
insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size);
break;
}
LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
dc->pc, size, dc->opcode, dc->src, dc->dst);
cpu_abort(CPU(dc->cpu), "Unhandled opcode");