target-aarch64: Generate fences for aarch64
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20160714202026.9727-14-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -1294,6 +1294,8 @@ static void gen_clrex(DisasContext *s, uint32_t insn)
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static void handle_sync(DisasContext *s, uint32_t insn,
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unsigned int op1, unsigned int op2, unsigned int crm)
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{
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TCGBar bar;
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if (op1 != 3) {
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unallocated_encoding(s);
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return;
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@ -1305,7 +1307,18 @@ static void handle_sync(DisasContext *s, uint32_t insn,
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return;
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case 4: /* DSB */
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case 5: /* DMB */
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/* We don't emulate caches so barriers are no-ops */
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switch (crm & 3) {
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case 1: /* MBReqTypes_Reads */
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bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST;
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break;
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case 2: /* MBReqTypes_Writes */
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bar = TCG_BAR_SC | TCG_MO_ST_ST;
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break;
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default: /* MBReqTypes_All */
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bar = TCG_BAR_SC | TCG_MO_ALL;
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break;
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}
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tcg_gen_mb(bar);
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return;
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case 6: /* ISB */
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/* We need to break the TB after this insn to execute
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@ -1934,7 +1947,13 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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if (!is_store) {
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s->is_ldex = true;
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gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
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if (is_lasr) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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}
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} else {
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if (is_lasr) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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}
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gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
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}
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} else {
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@ -1943,11 +1962,17 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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/* Generate ISS for non-exclusive accesses including LASR. */
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if (is_store) {
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if (is_lasr) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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}
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do_gpr_st(s, tcg_rt, tcg_addr, size,
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true, rt, iss_sf, is_lasr);
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} else {
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do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false,
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true, rt, iss_sf, is_lasr);
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if (is_lasr) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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}
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}
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}
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}
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