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target/riscv: remove RISCV_FEATURE_DEBUG

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RISCV_FEATURE_DEBUG will always follow the value defined by
cpu->cfg.debug flag. Read the flag instead.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-02-22 15:51:59 -03:00 committed by Palmer Dabbelt
parent 54bd9b6ec3
commit cdfb290569
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
5 changed files with 4 additions and 10 deletions
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6
target/riscv/cpu.c
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@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj)
set_default_nan_mode(1, &env->fp_status); set_default_nan_mode(1, &env->fp_status);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { if (cpu->cfg.debug) {
riscv_trigger_init(env); riscv_trigger_init(env);
} }
@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
} }
} }
if (cpu->cfg.debug) {
riscv_set_feature(env, RISCV_FEATURE_DEBUG);
}
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (cpu->cfg.ext_sstc) { if (cpu->cfg.ext_sstc) {

1
target/riscv/cpu.h
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@ -89,7 +89,6 @@ enum {
RISCV_FEATURE_MMU, RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP, RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP, RISCV_FEATURE_EPMP,
RISCV_FEATURE_DEBUG
}; };
/* Privileged specification version */ /* Privileged specification version */

2
target/riscv/cpu_helper.c
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@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
get_field(env->mstatus_hs, MSTATUS_VS)); get_field(env->mstatus_hs, MSTATUS_VS));
} }
if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { if (cpu->cfg.debug && !icount_enabled()) {
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
} }
#endif #endif

2
target/riscv/csr.c
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@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
static RISCVException debug(CPURISCVState *env, int csrno) static RISCVException debug(CPURISCVState *env, int csrno)
{ {
if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { if (riscv_cpu_cfg(env)->debug) {
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }

3
target/riscv/machine.c
View File

@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = {
static bool debug_needed(void *opaque) static bool debug_needed(void *opaque)
{ {
RISCVCPU *cpu = opaque; RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
return riscv_feature(env, RISCV_FEATURE_DEBUG); return cpu->cfg.debug;
} }
static int debug_post_load(void *opaque, int version_id) static int debug_post_load(void *opaque, int version_id)