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target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz

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Rename the function to match gen_gvec_fn_zzz,
and move to be adjacent.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-32-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-27 11:17:44 -07:00 committed by Peter Maydell
parent 50f6db5f23
commit cd54bbe662
1 changed files with 16 additions and 15 deletions
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31
target/arm/translate-sve.c
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@ -274,6 +274,12 @@ static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
return true;
}
static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn,
arg_rrr_esz *a)
{
return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
}
/* Invoke a vector expander on four Zregs. */
static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
int esz, int rd, int rn, int rm, int ra)
@ -370,29 +376,24 @@ const uint64_t pred_esz_masks[4] = {
*** SVE Logical - Unpredicated Group
*/
static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
{
return gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
}
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_and);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_and, a);
}
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_or);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_or, a);
}
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_xor);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_xor, a);
}
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_andc);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_andc, a);
}
static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh)
@ -707,32 +708,32 @@ static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_add);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_add, a);
}
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_sub);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sub, a);
}
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ssadd, a);
}
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sssub, a);
}
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_usadd, a);
}
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ussub, a);
}
/*