hw/block/pflash_cfi: Fix code style for checkpatch.pl
We are going to move this code, fix its style first. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210310170528.1184868-2-philmd@redhat.com>
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@ -115,7 +115,8 @@ static const VMStateDescription vmstate_pflash = {
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}
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};
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/* Perform a CFI query based on the bank width of the flash.
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/*
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* Perform a CFI query based on the bank width of the flash.
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* If this code is called we know we have a device_width set for
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* this flash.
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*/
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@ -125,7 +126,8 @@ static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset)
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uint32_t resp = 0;
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hwaddr boff;
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/* Adjust incoming offset to match expected device-width
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/*
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* Adjust incoming offset to match expected device-width
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* addressing. CFI query addresses are always specified in terms of
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* the maximum supported width of the device. This means that x8
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* devices and x8/x16 devices in x8 mode behave differently. For
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@ -141,7 +143,8 @@ static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset)
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if (boff >= sizeof(pfl->cfi_table)) {
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return 0;
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}
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/* Now we will construct the CFI response generated by a single
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/*
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* Now we will construct the CFI response generated by a single
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* device, then replicate that for all devices that make up the
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* bus. For wide parts used in x8 mode, CFI query responses
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* are different than native byte-wide parts.
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@ -185,7 +188,8 @@ static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset)
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uint32_t resp;
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hwaddr boff;
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/* Adjust incoming offset to match expected device-width
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/*
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* Adjust incoming offset to match expected device-width
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* addressing. Device ID read addresses are always specified in
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* terms of the maximum supported width of the device. This means
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* that x8 devices and x8/x16 devices in x8 mode behave
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@ -198,7 +202,8 @@ static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset)
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boff = offset >> (ctz32(pfl->bank_width) +
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ctz32(pfl->max_device_width) - ctz32(pfl->device_width));
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/* Mask off upper bits which may be used in to query block
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/*
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* Mask off upper bits which may be used in to query block
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* or sector lock status at other addresses.
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* Offsets 2/3 are block lock status, is not emulated.
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*/
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@ -297,7 +302,8 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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case 0x60: /* Block /un)lock */
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case 0x70: /* Status Register */
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case 0xe8: /* Write block */
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/* Status register read. Return status from each device in
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/*
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* Status register read. Return status from each device in
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* bank.
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*/
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ret = pfl->status;
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@ -308,7 +314,8 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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shift += pfl->device_width * 8;
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}
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} else if (!pfl->device_width && width > 2) {
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/* Handle 32 bit flash cases where device width is not
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/*
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* Handle 32 bit flash cases where device width is not
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* set. (Existing behavior before device width added.)
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*/
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ret |= pfl->status << 16;
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@ -340,7 +347,8 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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break;
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}
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} else {
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/* If we have a read larger than the bank_width, combine multiple
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/*
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* If we have a read larger than the bank_width, combine multiple
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* manufacturer/device ID queries into a single response.
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*/
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int i;
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@ -367,7 +375,8 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
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ret = 0;
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}
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} else {
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/* If we have a read larger than the bank_width, combine multiple
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/*
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* If we have a read larger than the bank_width, combine multiple
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* CFI queries into a single response.
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*/
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int i;
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@ -544,7 +553,8 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
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break;
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case 0xe8:
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/* Mask writeblock size based on device width, or bank width if
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/*
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* Mask writeblock size based on device width, or bank width if
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* device width not specified.
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*/
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/* FIXME check @offset, @width */
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@ -718,7 +728,8 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
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total_len = pfl->sector_len * pfl->nb_blocs;
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/* These are only used to expose the parameters of each device
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/*
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* These are only used to expose the parameters of each device
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* in the cfi_table[].
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*/
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num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1;
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@ -763,7 +774,8 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
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}
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}
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/* Default to devices being used at their maximum device width. This was
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/*
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* Default to devices being used at their maximum device width. This was
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* assumed before the device_width support was added.
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*/
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if (!pfl->max_device_width) {
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@ -100,7 +100,8 @@ struct PFlashCFI02 {
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uint16_t unlock_addr1;
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uint8_t cfi_table[0x4d];
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QEMUTimer timer;
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/* The device replicates the flash memory across its memory space. Emulate
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/*
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* The device replicates the flash memory across its memory space. Emulate
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* that by having a container (.mem) filled with an array of aliases
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* (.mem_mappings) pointing to the flash memory (.orig_mem).
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*/
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@ -884,8 +885,10 @@ static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
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pfl->cfi_table[0x28] = 0x02;
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pfl->cfi_table[0x29] = 0x00;
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/* Max number of bytes in multi-bytes write */
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/* XXX: disable buffered write as it's not supported */
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// pfl->cfi_table[0x2A] = 0x05;
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/*
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* XXX: disable buffered write as it's not supported
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* pfl->cfi_table[0x2A] = 0x05;
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*/
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pfl->cfi_table[0x2A] = 0x00;
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pfl->cfi_table[0x2B] = 0x00;
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/* Number of erase block regions */
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