bcm2836_control: add bcm2836 ARM control logic
This module is specific to the bcm2836 (Pi2). It implements the top level interrupt controller, and mailboxes used for inter-processor synchronisation. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrew Baumann
Peter Maydell
parent
7c62aeb82a
commit
cc28296d82
@ -24,7 +24,7 @@ obj-$(CONFIG_GRLIB) += grlib_irqmp.o
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obj-$(CONFIG_IOAPIC) += ioapic.o
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obj-$(CONFIG_OMAP) += omap_intc.o
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obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
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obj-$(CONFIG_RASPI) += bcm2835_ic.o
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obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
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obj-$(CONFIG_SH4) += sh_intc.o
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obj-$(CONFIG_XICS) += xics.o
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obj-$(CONFIG_XICS_KVM) += xics_kvm.o
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303
hw/intc/bcm2836_control.c
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303
hw/intc/bcm2836_control.c
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@ -0,0 +1,303 @@
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/*
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* Rasperry Pi 2 emulation ARM control logic module.
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* Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade
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* This code is licensed under the GNU GPLv2 and later.
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*
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* At present, only implements interrupt routing, and mailboxes (i.e.,
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* not local timer, PMU interrupt, or AXI counters).
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*
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* Ref:
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* https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
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*/
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#include "hw/intc/bcm2836_control.h"
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#define REG_GPU_ROUTE 0x0c
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#define REG_TIMERCONTROL 0x40
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#define REG_MBOXCONTROL 0x50
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#define REG_IRQSRC 0x60
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#define REG_FIQSRC 0x70
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#define REG_MBOX0_WR 0x80
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#define REG_MBOX0_RDCLR 0xc0
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#define REG_LIMIT 0x100
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#define IRQ_BIT(cntrl, num) (((cntrl) & (1 << (num))) != 0)
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#define FIQ_BIT(cntrl, num) (((cntrl) & (1 << ((num) + 4))) != 0)
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#define IRQ_CNTPSIRQ 0
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#define IRQ_CNTPNSIRQ 1
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#define IRQ_CNTHPIRQ 2
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#define IRQ_CNTVIRQ 3
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#define IRQ_MAILBOX0 4
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#define IRQ_MAILBOX1 5
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#define IRQ_MAILBOX2 6
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#define IRQ_MAILBOX3 7
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#define IRQ_GPU 8
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#define IRQ_PMU 9
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#define IRQ_AXI 10
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#define IRQ_TIMER 11
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#define IRQ_MAX IRQ_TIMER
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static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq,
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uint32_t controlreg, uint8_t controlidx)
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{
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if (FIQ_BIT(controlreg, controlidx)) {
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/* deliver a FIQ */
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s->fiqsrc[core] |= (uint32_t)1 << irq;
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} else if (IRQ_BIT(controlreg, controlidx)) {
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/* deliver an IRQ */
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s->irqsrc[core] |= (uint32_t)1 << irq;
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} else {
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/* the interrupt is masked */
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}
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}
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/* Update interrupts. */
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static void bcm2836_control_update(BCM2836ControlState *s)
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{
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int i, j;
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/* reset pending IRQs/FIQs */
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for (i = 0; i < BCM2836_NCORES; i++) {
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s->irqsrc[i] = s->fiqsrc[i] = 0;
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}
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/* apply routing logic, update status regs */
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if (s->gpu_irq) {
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assert(s->route_gpu_irq < BCM2836_NCORES);
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s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU;
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}
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if (s->gpu_fiq) {
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assert(s->route_gpu_fiq < BCM2836_NCORES);
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s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU;
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}
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for (i = 0; i < BCM2836_NCORES; i++) {
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/* handle local timer interrupts for this core */
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if (s->timerirqs[i]) {
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assert(s->timerirqs[i] < (1 << (IRQ_CNTVIRQ + 1))); /* sane mask? */
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for (j = 0; j <= IRQ_CNTVIRQ; j++) {
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if ((s->timerirqs[i] & (1 << j)) != 0) {
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/* local interrupt j is set */
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deliver_local(s, i, j, s->timercontrol[i], j);
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}
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}
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}
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/* handle mailboxes for this core */
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for (j = 0; j < BCM2836_MBPERCORE; j++) {
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if (s->mailboxes[i * BCM2836_MBPERCORE + j] != 0) {
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/* mailbox j is set */
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deliver_local(s, i, j + IRQ_MAILBOX0, s->mailboxcontrol[i], j);
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}
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}
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}
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/* call set_irq appropriately for each output */
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for (i = 0; i < BCM2836_NCORES; i++) {
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qemu_set_irq(s->irq[i], s->irqsrc[i] != 0);
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qemu_set_irq(s->fiq[i], s->fiqsrc[i] != 0);
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}
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}
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static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq,
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int level)
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{
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BCM2836ControlState *s = opaque;
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assert(core >= 0 && core < BCM2836_NCORES);
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assert(local_irq >= 0 && local_irq <= IRQ_CNTVIRQ);
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s->timerirqs[core] = deposit32(s->timerirqs[core], local_irq, 1, !!level);
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bcm2836_control_update(s);
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}
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/* XXX: the following wrapper functions are a kludgy workaround,
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* needed because I can't seem to pass useful information in the "irq"
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* parameter when using named interrupts. Feel free to clean this up!
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*/
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static void bcm2836_control_set_local_irq0(void *opaque, int core, int level)
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{
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bcm2836_control_set_local_irq(opaque, core, 0, level);
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}
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static void bcm2836_control_set_local_irq1(void *opaque, int core, int level)
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{
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bcm2836_control_set_local_irq(opaque, core, 1, level);
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}
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static void bcm2836_control_set_local_irq2(void *opaque, int core, int level)
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{
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bcm2836_control_set_local_irq(opaque, core, 2, level);
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}
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static void bcm2836_control_set_local_irq3(void *opaque, int core, int level)
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{
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bcm2836_control_set_local_irq(opaque, core, 3, level);
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}
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static void bcm2836_control_set_gpu_irq(void *opaque, int irq, int level)
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{
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BCM2836ControlState *s = opaque;
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s->gpu_irq = level;
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bcm2836_control_update(s);
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}
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static void bcm2836_control_set_gpu_fiq(void *opaque, int irq, int level)
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{
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BCM2836ControlState *s = opaque;
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s->gpu_fiq = level;
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bcm2836_control_update(s);
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}
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static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
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{
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BCM2836ControlState *s = opaque;
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if (offset == REG_GPU_ROUTE) {
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assert(s->route_gpu_fiq < BCM2836_NCORES
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&& s->route_gpu_irq < BCM2836_NCORES);
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return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq;
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} else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
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return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2];
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} else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
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return s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2];
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} else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) {
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return s->irqsrc[(offset - REG_IRQSRC) >> 2];
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} else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) {
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return s->fiqsrc[(offset - REG_FIQSRC) >> 2];
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} else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
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return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
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__func__, offset);
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return 0;
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}
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}
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static void bcm2836_control_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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BCM2836ControlState *s = opaque;
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if (offset == REG_GPU_ROUTE) {
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s->route_gpu_irq = val & 0x3;
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s->route_gpu_fiq = (val >> 2) & 0x3;
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} else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
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s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff;
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} else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
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s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2] = val & 0xff;
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} else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) {
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s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val;
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} else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
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s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
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__func__, offset);
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return;
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}
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bcm2836_control_update(s);
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}
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static const MemoryRegionOps bcm2836_control_ops = {
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.read = bcm2836_control_read,
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.write = bcm2836_control_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void bcm2836_control_reset(DeviceState *d)
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{
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BCM2836ControlState *s = BCM2836_CONTROL(d);
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int i;
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s->route_gpu_irq = s->route_gpu_fiq = 0;
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for (i = 0; i < BCM2836_NCORES; i++) {
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s->timercontrol[i] = 0;
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s->mailboxcontrol[i] = 0;
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}
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for (i = 0; i < BCM2836_NCORES * BCM2836_MBPERCORE; i++) {
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s->mailboxes[i] = 0;
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}
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}
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static void bcm2836_control_init(Object *obj)
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{
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BCM2836ControlState *s = BCM2836_CONTROL(obj);
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DeviceState *dev = DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &bcm2836_control_ops, s,
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TYPE_BCM2836_CONTROL, REG_LIMIT);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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/* inputs from each CPU core */
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qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq0, "cntpsirq",
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BCM2836_NCORES);
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qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq1, "cntpnsirq",
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BCM2836_NCORES);
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qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq2, "cnthpirq",
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BCM2836_NCORES);
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qdev_init_gpio_in_named(dev, bcm2836_control_set_local_irq3, "cntvirq",
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BCM2836_NCORES);
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/* IRQ and FIQ inputs from upstream bcm2835 controller */
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qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_irq, "gpu-irq", 1);
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qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu-fiq", 1);
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/* outputs to CPU cores */
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qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES);
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qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES);
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}
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static const VMStateDescription vmstate_bcm2836_control = {
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.name = TYPE_BCM2836_CONTROL,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState,
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BCM2836_NCORES * BCM2836_MBPERCORE),
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VMSTATE_UINT8(route_gpu_irq, BCM2836ControlState),
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VMSTATE_UINT8(route_gpu_fiq, BCM2836ControlState),
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VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES),
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VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState,
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BCM2836_NCORES),
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VMSTATE_END_OF_LIST()
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}
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};
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static void bcm2836_control_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = bcm2836_control_reset;
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dc->vmsd = &vmstate_bcm2836_control;
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}
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static TypeInfo bcm2836_control_info = {
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.name = TYPE_BCM2836_CONTROL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BCM2836ControlState),
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.class_init = bcm2836_control_class_init,
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.instance_init = bcm2836_control_init,
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};
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static void bcm2836_control_register_types(void)
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{
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type_register_static(&bcm2836_control_info);
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}
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type_init(bcm2836_control_register_types)
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51
include/hw/intc/bcm2836_control.h
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51
include/hw/intc/bcm2836_control.h
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@ -0,0 +1,51 @@
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/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* This code is licensed under the GNU GPLv2 and later.
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*/
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#ifndef BCM2836_CONTROL_H
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#define BCM2836_CONTROL_H
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#include "hw/sysbus.h"
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/* 4 mailboxes per core, for 16 total */
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#define BCM2836_NCORES 4
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#define BCM2836_MBPERCORE 4
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#define TYPE_BCM2836_CONTROL "bcm2836-control"
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#define BCM2836_CONTROL(obj) \
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OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL)
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typedef struct BCM2836ControlState {
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/*< private >*/
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SysBusDevice busdev;
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/*< public >*/
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MemoryRegion iomem;
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/* mailbox state */
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uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
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/* interrupt routing/control registers */
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uint8_t route_gpu_irq, route_gpu_fiq;
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uint32_t timercontrol[BCM2836_NCORES];
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uint32_t mailboxcontrol[BCM2836_NCORES];
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/* interrupt status regs (derived from input pins; not visible to user) */
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bool gpu_irq, gpu_fiq;
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uint8_t timerirqs[BCM2836_NCORES];
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/* interrupt source registers, post-routing (also input-derived; visible) */
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uint32_t irqsrc[BCM2836_NCORES];
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uint32_t fiqsrc[BCM2836_NCORES];
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/* outputs to CPU cores */
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qemu_irq irq[BCM2836_NCORES];
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qemu_irq fiq[BCM2836_NCORES];
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} BCM2836ControlState;
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#endif
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