mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

gdbstub: Implement write memory (M pkt) with new infra

Browse Source 
Signed-off-by: Jon Doron <arilou@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20190529064148.19856-11-arilou@gmail.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
This commit is contained in:
Jon Doron 2019-05-29 09:41:38 +03:00 committed by Alex Bennée
parent 5d0e57bd68
commit cc0ecc7890
1 changed files with 33 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
gdbstub.c
View File

@ -1706,6 +1706,31 @@ static void handle_get_reg(GdbCmdContext *gdb_ctx, void *user_ctx)
put_packet(gdb_ctx->s, gdb_ctx->str_buf); put_packet(gdb_ctx->s, gdb_ctx->str_buf);
} }
static void handle_write_mem(GdbCmdContext *gdb_ctx, void *user_ctx)
{
if (gdb_ctx->num_params != 3) {
put_packet(gdb_ctx->s, "E22");
return;
}
/* hextomem() reads 2*len bytes */
if (gdb_ctx->params[1].val_ull > strlen(gdb_ctx->params[2].data) / 2) {
put_packet(gdb_ctx->s, "E22");
return;
}
hextomem(gdb_ctx->mem_buf, gdb_ctx->params[2].data,
gdb_ctx->params[1].val_ull);
if (target_memory_rw_debug(gdb_ctx->s->g_cpu, gdb_ctx->params[0].val_ull,
gdb_ctx->mem_buf,
gdb_ctx->params[1].val_ull, true)) {
put_packet(gdb_ctx->s, "E14");
return;
}
put_packet(gdb_ctx->s, "OK");
}
static int gdb_handle_packet(GDBState *s, const char *line_buf) static int gdb_handle_packet(GDBState *s, const char *line_buf)
{ {
CPUState *cpu; CPUState *cpu;
@ -1914,24 +1939,14 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
} }
break; break;
case 'M': case 'M':
addr = strtoull(p, (char **)&p, 16); {
if (*p == ',') static const GdbCmdParseEntry write_mem_cmd_desc = {
p++; .handler = handle_write_mem,
len = strtoull(p, (char **)&p, 16); .cmd = "M",
if (*p == ':') .cmd_startswith = 1,
p++; .schema = "L,L:s0"
};
/* hextomem() reads 2*len bytes */ cmd_parser = &write_mem_cmd_desc;
if (len > strlen(p) / 2) {
put_packet (s, "E22");
break;
}
hextomem(mem_buf, p, len);
if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len,
true) != 0) {
put_packet(s, "E14");
} else {
put_packet(s, "OK");
} }
break; break;
case 'p': case 'p':