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tcg/riscv: Implement vector shi/s/v ops

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Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241007025700.47259-11-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
TANG Tiancheng 2024-10-07 10:56:58 +08:00 committed by Richard Henderson
parent 1631f19b04
commit cbde22f18b
3 changed files with 80 additions and 3 deletions
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1
tcg/riscv/tcg-target-con-set.h
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@ -24,6 +24,7 @@ C_O2_I4(r, r, rZ, rZ, rM, rM)
C_O0_I2(v, r) C_O0_I2(v, r)
C_O1_I1(v, r) C_O1_I1(v, r)
C_O1_I1(v, v) C_O1_I1(v, v)
C_O1_I2(v, v, r)
C_O1_I2(v, v, v) C_O1_I2(v, v, v)
C_O1_I2(v, vK, v) C_O1_I2(v, vK, v)
C_O1_I2(v, v, vK) C_O1_I2(v, v, vK)

76
tcg/riscv/tcg-target.c.inc
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@ -326,6 +326,16 @@ typedef enum {
OPC_VMSGT_VI = 0x7c000057 | V_OPIVI, OPC_VMSGT_VI = 0x7c000057 | V_OPIVI,
OPC_VMSGT_VX = 0x7c000057 | V_OPIVX, OPC_VMSGT_VX = 0x7c000057 | V_OPIVX,
OPC_VSLL_VV = 0x94000057 | V_OPIVV,
OPC_VSLL_VI = 0x94000057 | V_OPIVI,
OPC_VSLL_VX = 0x94000057 | V_OPIVX,
OPC_VSRL_VV = 0xa0000057 | V_OPIVV,
OPC_VSRL_VI = 0xa0000057 | V_OPIVI,
OPC_VSRL_VX = 0xa0000057 | V_OPIVX,
OPC_VSRA_VV = 0xa4000057 | V_OPIVV,
OPC_VSRA_VI = 0xa4000057 | V_OPIVI,
OPC_VSRA_VX = 0xa4000057 | V_OPIVX,
OPC_VMV_V_V = 0x5e000057 | V_OPIVV, OPC_VMV_V_V = 0x5e000057 | V_OPIVV,
OPC_VMV_V_I = 0x5e000057 | V_OPIVI, OPC_VMV_V_I = 0x5e000057 | V_OPIVI,
OPC_VMV_V_X = 0x5e000057 | V_OPIVX, OPC_VMV_V_X = 0x5e000057 | V_OPIVX,
@ -1551,6 +1561,17 @@ static void tcg_out_cmpsel(TCGContext *s, TCGType type, unsigned vece,
} }
} }
static void tcg_out_vshifti(TCGContext *s, RISCVInsn opc_vi, RISCVInsn opc_vx,
TCGReg dst, TCGReg src, unsigned imm)
{
if (imm < 32) {
tcg_out_opc_vi(s, opc_vi, dst, src, imm);
} else {
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP0, imm);
tcg_out_opc_vx(s, opc_vx, dst, src, TCG_REG_TMP0);
}
}
static void init_setting_vtype(TCGContext *s) static void init_setting_vtype(TCGContext *s)
{ {
s->riscv_cur_type = TCG_TYPE_COUNT; s->riscv_cur_type = TCG_TYPE_COUNT;
@ -2431,6 +2452,42 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
set_vtype_len_sew(s, type, vece); set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv_vi(s, OPC_VMINU_VV, OPC_VMINU_VI, a0, a1, a2, c2); tcg_out_opc_vv_vi(s, OPC_VMINU_VV, OPC_VMINU_VI, a0, a1, a2, c2);
break; break;
case INDEX_op_shls_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vx(s, OPC_VSLL_VX, a0, a1, a2);
break;
case INDEX_op_shrs_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, a2);
break;
case INDEX_op_sars_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vx(s, OPC_VSRA_VX, a0, a1, a2);
break;
case INDEX_op_shlv_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2);
break;
case INDEX_op_shrv_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2);
break;
case INDEX_op_sarv_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2);
break;
case INDEX_op_shli_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, a0, a1, a2);
break;
case INDEX_op_shri_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, a2);
break;
case INDEX_op_sari_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_vshifti(s, OPC_VSRA_VI, OPC_VSRA_VX, a0, a1, a2);
break;
case INDEX_op_cmp_vec: case INDEX_op_cmp_vec:
tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2,
-1, true, 0, true); -1, true, 0, true);
@ -2471,6 +2528,15 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_smin_vec: case INDEX_op_smin_vec:
case INDEX_op_umax_vec: case INDEX_op_umax_vec:
case INDEX_op_umin_vec: case INDEX_op_umin_vec:
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
case INDEX_op_shri_vec:
case INDEX_op_shli_vec:
case INDEX_op_sari_vec:
case INDEX_op_cmp_vec: case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec: case INDEX_op_cmpsel_vec:
return 1; return 1;
@ -2626,6 +2692,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O1_I1(v, r); return C_O1_I1(v, r);
case INDEX_op_neg_vec: case INDEX_op_neg_vec:
case INDEX_op_not_vec: case INDEX_op_not_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
return C_O1_I1(v, v); return C_O1_I1(v, v);
case INDEX_op_add_vec: case INDEX_op_add_vec:
case INDEX_op_and_vec: case INDEX_op_and_vec:
@ -2643,7 +2712,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_sub_vec: case INDEX_op_sub_vec:
return C_O1_I2(v, vK, v); return C_O1_I2(v, vK, v);
case INDEX_op_mul_vec: case INDEX_op_mul_vec:
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
return C_O1_I2(v, v, v); return C_O1_I2(v, v, v);
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
return C_O1_I2(v, v, r);
case INDEX_op_cmp_vec: case INDEX_op_cmp_vec:
return C_O1_I2(v, v, vL); return C_O1_I2(v, v, vL);
case INDEX_op_cmpsel_vec: case INDEX_op_cmpsel_vec:

6
tcg/riscv/tcg-target.h
View File

@ -157,9 +157,9 @@ typedef enum {
#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_minmax_vec 1