mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

msi: Invoke msi/msix_reset from PCI core

Browse Source 
There is no point in pushing this burden to the devices, they tend to
forget to call them (like intel-hda, ahci, xhci did). Instead, reset
functions are now called from pci_device_reset. They do nothing if
MSI/MSI-X is not in use.

CC: Alexander Graf <agraf@suse.de>
CC: Gerd Hoffmann <kraxel@redhat.com>
CC: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jan Kiszka 2012-05-15 20:09:56 -03:00 committed by Michael S. Tsirkin
parent 520064c8b1
commit cbd2d4342b
10 changed files with 11 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hw/ide/ich.c
View File

@ -88,7 +88,6 @@ static void pci_ich9_reset(DeviceState *dev)
{
struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev);
msi_reset(&d->card);
ahci_reset(&d->ahci);
}

3
hw/intel-hda.c
View File

@ -1107,9 +1107,6 @@ static void intel_hda_reset(DeviceState *dev)
DeviceState *qdev;
HDACodecDevice *cdev;
if (d->msi) {
msi_reset(&d->pci);
}
intel_hda_regs_reset(d);
d->wall_base_ns = qemu_get_clock_ns(vm_clock);

2
hw/ioh3420.c
View File

@ -81,7 +81,7 @@ static void ioh3420_write_config(PCIDevice *d,
static void ioh3420_reset(DeviceState *qdev)
{
PCIDevice *d = PCI_DEVICE(qdev);
msi_reset(d);
ioh3420_aer_vector_update(d);
pcie_cap_root_reset(d);
pcie_cap_deverr_reset(d);

1
hw/ivshmem.c
View File

@ -530,7 +530,6 @@ static void ivshmem_reset(DeviceState *d)
IVShmemState *s = DO_UPCAST(IVShmemState, dev.qdev, d);
s->intrstatus = 0;
msix_reset(&s->dev);
ivshmem_use_msix(s);
return;
}

5
hw/pci.c
View File

@ -31,6 +31,8 @@
#include "loader.h"
#include "range.h"
#include "qmp-commands.h"
#include "msi.h"
#include "msix.h"
//#define DEBUG_PCI
#ifdef DEBUG_PCI
@ -188,6 +190,9 @@ void pci_device_reset(PCIDevice *dev)
}
}
pci_update_mappings(dev);
msi_reset(dev);
msix_reset(dev);
}
/*

10
hw/pci_bridge.c
View File

@ -254,8 +254,9 @@ void pci_bridge_disable_base_limit(PCIDevice *dev)
}
/* reset bridge specific configuration registers */
void pci_bridge_reset_reg(PCIDevice *dev)
void pci_bridge_reset(DeviceState *qdev)
{
PCIDevice *dev = PCI_DEVICE(qdev);
uint8_t *conf = dev->config;
conf[PCI_PRIMARY_BUS] = 0;
@ -291,13 +292,6 @@ void pci_bridge_reset_reg(PCIDevice *dev)
pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
}
/* default reset function for PCI-to-PCI bridge */
void pci_bridge_reset(DeviceState *qdev)
{
PCIDevice *dev = PCI_DEVICE(qdev);
pci_bridge_reset_reg(dev);
}
/* default qdev initialization function for PCI-to-PCI bridge */
int pci_bridge_initfn(PCIDevice *dev)
{

4
hw/pci_bridge_dev.c
View File

@ -119,10 +119,8 @@ static void pci_bridge_dev_write_config(PCIDevice *d,
static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
{
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
pci_bridge_reset(qdev);
if (msi_present(dev)) {
msi_reset(dev);
}
shpc_reset(dev);
}

1
hw/virtio-pci.c
View File

@ -278,7 +278,6 @@ void virtio_pci_reset(DeviceState *d)
VirtIOPCIProxy *proxy = container_of(d, VirtIOPCIProxy, pci_dev.qdev);
virtio_pci_stop_ioeventfd(proxy);
virtio_reset(proxy->vdev);
msix_reset(&proxy->pci_dev);
proxy->flags &= ~VIRTIO_PCI_FLAG_BUS_MASTER_BUG;
}

2
hw/xio3130_downstream.c
View File

@ -48,7 +48,7 @@ static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
static void xio3130_downstream_reset(DeviceState *qdev)
{
PCIDevice *d = PCI_DEVICE(qdev);
msi_reset(d);
pcie_cap_deverr_reset(d);
pcie_cap_slot_reset(d);
pcie_cap_ari_reset(d);

2
hw/xio3130_upstream.c
View File

@ -47,7 +47,7 @@ static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
static void xio3130_upstream_reset(DeviceState *qdev)
{
PCIDevice *d = PCI_DEVICE(qdev);
msi_reset(d);
pci_bridge_reset(qdev);
pcie_cap_deverr_reset(d);
}