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target-mips: optimize gen_movcf_*()

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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6957 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-03-29 15:45:02 +00:00
parent af58f9ca43
commit cbc37b28b3
1 changed files with 23 additions and 51 deletions
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74
target-mips/translate.c
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@ -5722,98 +5722,70 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
static inline void gen_movcf_s (int fs, int fd, int cc, int tf) static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
{ {
uint32_t ccbit;
int cond; int cond;
TCGv_i32 r_tmp1 = tcg_temp_new_i32(); TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 fp0 = tcg_temp_local_new_i32();
int l1 = gen_new_label(); int l1 = gen_new_label();
if (cc)
ccbit = 1 << (24 + cc);
else
ccbit = 1 << 23;
if (tf) if (tf)
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
else else
cond = TCG_COND_NE; cond = TCG_COND_NE;
gen_load_fpr32(fp0, fd); tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit); tcg_gen_brcondi_i32(cond, t0, 0, l1);
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); gen_load_fpr32(t0, fs);
tcg_temp_free_i32(r_tmp1); gen_store_fpr32(t0, fd);
gen_load_fpr32(fp0, fs);
gen_set_label(l1); gen_set_label(l1);
gen_store_fpr32(fp0, fd); tcg_temp_free_i32(t0);
tcg_temp_free_i32(fp0);
} }
static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
{ {
uint32_t ccbit;
int cond; int cond;
TCGv_i32 r_tmp1 = tcg_temp_new_i32(); TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i64 fp0 = tcg_temp_local_new_i64(); TCGv_i64 fp0;
int l1 = gen_new_label(); int l1 = gen_new_label();
if (cc)
ccbit = 1 << (24 + cc);
else
ccbit = 1 << 23;
if (tf) if (tf)
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
else else
cond = TCG_COND_NE; cond = TCG_COND_NE;
gen_load_fpr64(ctx, fp0, fd); tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit); tcg_gen_brcondi_i32(cond, t0, 0, l1);
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); fp0 = tcg_temp_local_new_i64();
tcg_temp_free_i32(r_tmp1);
gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp0, fs);
gen_set_label(l1);
gen_store_fpr64(ctx, fp0, fd); gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp0);
gen_set_label(l1);
tcg_temp_free_i32(t0);
} }
static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) static inline void gen_movcf_ps (int fs, int fd, int cc, int tf)
{ {
uint32_t ccbit1, ccbit2;
int cond; int cond;
TCGv_i32 r_tmp1 = tcg_temp_new_i32(); TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 fp0 = tcg_temp_local_new_i32();
int l1 = gen_new_label(); int l1 = gen_new_label();
int l2 = gen_new_label(); int l2 = gen_new_label();
if (cc) {
ccbit1 = 1 << (24 + cc);
ccbit2 = 1 << (25 + cc);
} else {
ccbit1 = 1 << 23;
ccbit2 = 1 << 25;
}
if (tf) if (tf)
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
else else
cond = TCG_COND_NE; cond = TCG_COND_NE;
gen_load_fpr32(fp0, fd); tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit1); tcg_gen_brcondi_i32(cond, t0, 0, l1);
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); gen_load_fpr32(t0, fs);
gen_load_fpr32(fp0, fs); gen_store_fpr32(t0, fd);
gen_set_label(l1); gen_set_label(l1);
gen_store_fpr32(fp0, fd);
gen_load_fpr32h(fp0, fd); tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc+1));
tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit2); tcg_gen_brcondi_i32(cond, t0, 0, l2);
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l2); gen_load_fpr32h(t0, fs);
gen_load_fpr32h(fp0, fs); gen_store_fpr32h(t0, fd);
gen_set_label(l2); gen_set_label(l2);
gen_store_fpr32h(fp0, fd);
tcg_temp_free_i32(r_tmp1); tcg_temp_free_i32(t0);
tcg_temp_free_i32(fp0);
} }