esp.c: fix premature end of phase logic esp_command_complete
There are two cases here: the first is when the TI command underflows, in which case we raise INTR_BS to indicate an early change of phase, and the second is when the TI command overflows because the host requested a transfer for more data than is available. In the latter case force TC to zero so that the TI completion logic executes correctly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Helge Deller <deller@gmx.de> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240112125420.514425-30-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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@ -887,7 +887,6 @@ void esp_command_complete(SCSIRequest *req, size_t resid)
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if (s->ti_size != 0) {
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trace_esp_command_complete_unexpected();
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}
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s->ti_size = 0;
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}
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s->async_len = 0;
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@ -897,13 +896,26 @@ void esp_command_complete(SCSIRequest *req, size_t resid)
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s->status = req->status;
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/*
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* If the transfer is finished, switch to status phase. For non-DMA
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* transfers from the target the last byte is still in the FIFO
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* Switch to status phase. For non-DMA transfers from the target the last
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* byte is still in the FIFO
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*/
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if (s->ti_size == 0) {
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esp_set_phase(s, STAT_ST);
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if (s->ti_size == 0) {
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/*
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* Transfer complete: force TC to zero just in case a TI command was
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* requested for more data than the command returns (Solaris 8 does
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* this)
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*/
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esp_set_tc(s, 0);
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esp_dma_done(s);
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esp_lower_drq(s);
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} else {
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/*
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* Transfer truncated: raise INTR_BS to indicate early change of
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* phase
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*/
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s->rregs[ESP_RINTR] |= INTR_BS;
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esp_raise_irq(s);
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s->ti_size = 0;
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}
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if (s->current_req) {
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