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hw/intc/arm_gicv3_cpuif: Add cast to match the documentation

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The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved.

Add an explicit cast to match the documentation.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Cc: qemu-stable@nongnu.org
Fixes: c3f21b065a ("hw/intc/arm_gicv3_cpuif: Support vLPIs")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 3db74afec3)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Alexandra Diupina 2024-10-14 17:05:51 +01:00 committed by Michael Tokarev
parent f1112c6776
commit cb5239e607
1 changed files with 1 additions and 1 deletions
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hw/intc/arm_gicv3_cpuif.c
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@ -751,7 +751,7 @@ static void icv_activate_vlpi(GICv3CPUState *cs)
int regno = aprbit / 32; int regno = aprbit / 32;
int regbit = aprbit % 32; int regbit = aprbit % 32;
cs->ich_apr[cs->hppvlpi.grp][regno] |= (1 << regbit); cs->ich_apr[cs->hppvlpi.grp][regno] |= (1U << regbit);
gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0); gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0);
} }