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mainstone: convert FPGA emulation code to use QDev/SysBus

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Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
This commit is contained in:
Dmitry Eremin-Solenikov 2011-02-12 03:15:24 +03:00 committed by Andrzej Zaborowski
parent 43d91709c1
commit cb380f615c
3 changed files with 55 additions and 55 deletions
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11
hw/mainstone.c
View File

@ -18,6 +18,7 @@
#include "sysemu.h"
#include "flash.h"
#include "blockdev.h"
#include "sysbus.h"
static struct keymap map[0xE0] = {
[0 ... 0xDF] = { -1, -1 },
@ -77,7 +78,7 @@ static void mainstone_common_init(ram_addr_t ram_size,
uint32_t sector_len = 256 * 1024;
target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *cpu;
qemu_irq *mst_irq;
DeviceState *mst_irq;
DriveInfo *dinfo;
int i;
int be;
@ -117,16 +118,18 @@ static void mainstone_common_init(ram_addr_t ram_size,
}
}
mst_irq = mst_irq_init(MST_FPGA_PHYS, cpu->pic[PXA2XX_PIC_GPIO_0]);
mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
cpu->pic[PXA2XX_PIC_GPIO_0]);
/* setup keypad */
printf("map addr %p\n", &map);
pxa27x_register_keypad(cpu->kp, map, 0xe0);
/* MMC/SD host */
pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);
pxa2xx_mmci_handlers(cpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
smc91c111_init(&nd_table[0], MST_ETH_PHYS,
qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
mainstone_binfo.kernel_filename = kernel_filename;
mainstone_binfo.kernel_cmdline = kernel_cmdline;

3
hw/mainstone.h
View File

@ -32,7 +32,4 @@
#define S1_STSCHG_IRQ 14
#define S1_IRQ 15
extern qemu_irq
*mst_irq_init(uint32_t base, qemu_irq irq);
#endif /* __MAINSTONE_H__ */

96
hw/mst_fpga.c
View File

@ -8,7 +8,7 @@
* This code is licensed under the GNU GPL v2.
*/
#include "hw.h"
#include "mainstone.h"
#include "sysbus.h"
/* Mainstone FPGA for extern irqs */
#define FPGA_GPIO_PIN 0
@ -27,8 +27,9 @@
#define MST_PCMCIA1 0xe4
typedef struct mst_irq_state{
SysBusDevice busdev;
qemu_irq parent;
qemu_irq *pins;
uint32_t prev_level;
uint32_t leddat1;
@ -163,68 +164,67 @@ static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
mst_fpga_writeb,
};
static void
mst_fpga_save(QEMUFile *f, void *opaque)
{
struct mst_irq_state *s = (mst_irq_state *) opaque;
qemu_put_be32s(f, &s->prev_level);
qemu_put_be32s(f, &s->leddat1);
qemu_put_be32s(f, &s->leddat2);
qemu_put_be32s(f, &s->ledctrl);
qemu_put_be32s(f, &s->gpswr);
qemu_put_be32s(f, &s->mscwr1);
qemu_put_be32s(f, &s->mscwr2);
qemu_put_be32s(f, &s->mscwr3);
qemu_put_be32s(f, &s->mscrd);
qemu_put_be32s(f, &s->intmskena);
qemu_put_be32s(f, &s->intsetclr);
qemu_put_be32s(f, &s->pcmcia0);
qemu_put_be32s(f, &s->pcmcia1);
}
static int
mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
static int mst_fpga_post_load(void *opaque, int version_id)
{
mst_irq_state *s = (mst_irq_state *) opaque;
qemu_get_be32s(f, &s->prev_level);
qemu_get_be32s(f, &s->leddat1);
qemu_get_be32s(f, &s->leddat2);
qemu_get_be32s(f, &s->ledctrl);
qemu_get_be32s(f, &s->gpswr);
qemu_get_be32s(f, &s->mscwr1);
qemu_get_be32s(f, &s->mscwr2);
qemu_get_be32s(f, &s->mscwr3);
qemu_get_be32s(f, &s->mscrd);
qemu_get_be32s(f, &s->intmskena);
qemu_get_be32s(f, &s->intsetclr);
qemu_get_be32s(f, &s->pcmcia0);
qemu_get_be32s(f, &s->pcmcia1);
qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
return 0;
}
qemu_irq *mst_irq_init(uint32_t base, qemu_irq irq)
static int mst_fpga_init(SysBusDevice *dev)
{
mst_irq_state *s;
int iomemtype;
qemu_irq *qi;
s = (mst_irq_state *)
qemu_mallocz(sizeof(mst_irq_state));
s = FROM_SYSBUS(mst_irq_state, dev);
s->parent = irq;
sysbus_init_irq(dev, &s->parent);
/* alloc the external 16 irqs */
qi = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
s->pins = qi;
qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
iomemtype = cpu_register_io_memory(mst_fpga_readfn,
mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
mst_fpga_load, s);
return qi;
sysbus_init_mmio(dev, 0x00100000, iomemtype);
return 0;
}
static VMStateDescription vmstate_mst_fpga_regs = {
.name = "mainstone_fpga",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.post_load = mst_fpga_post_load,
.fields = (VMStateField []) {
VMSTATE_UINT32(prev_level, mst_irq_state),
VMSTATE_UINT32(leddat1, mst_irq_state),
VMSTATE_UINT32(leddat2, mst_irq_state),
VMSTATE_UINT32(ledctrl, mst_irq_state),
VMSTATE_UINT32(gpswr, mst_irq_state),
VMSTATE_UINT32(mscwr1, mst_irq_state),
VMSTATE_UINT32(mscwr2, mst_irq_state),
VMSTATE_UINT32(mscwr3, mst_irq_state),
VMSTATE_UINT32(mscrd, mst_irq_state),
VMSTATE_UINT32(intmskena, mst_irq_state),
VMSTATE_UINT32(intsetclr, mst_irq_state),
VMSTATE_UINT32(pcmcia0, mst_irq_state),
VMSTATE_UINT32(pcmcia1, mst_irq_state),
VMSTATE_END_OF_LIST(),
},
};
static SysBusDeviceInfo mst_fpga_info = {
.init = mst_fpga_init,
.qdev.name = "mainstone-fpga",
.qdev.desc = "Mainstone II FPGA",
.qdev.size = sizeof(mst_irq_state),
.qdev.vmsd = &vmstate_mst_fpga_regs,
};
static void mst_fpga_register(void)
{
sysbus_register_withprop(&mst_fpga_info);
}
device_init(mst_fpga_register);