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target/riscv: Use aesenc_SB_SR_AK 

This implements the AES64ES instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-06-01 23:22:20 -07:00
parent bdb01515ed
commit cad26538e8
1 changed files with 9 additions and 1 deletions
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10
target/riscv/crypto_helper.c
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@ -22,6 +22,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "crypto/aes.h"
#include "crypto/aes-round.h"
#include "crypto/sm4.h"
#define AES_XTIME(a) \
@ -136,6 +137,8 @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0)
static const AESState aes_zero = { };
static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
bool enc, bool mix)
{
@ -200,7 +203,12 @@ target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
{
return aes64_operation(rs1, rs2, true, false);
AESState t;
t.d[HOST_BIG_ENDIAN] = rs1;
t.d[!HOST_BIG_ENDIAN] = rs2;
aesenc_SB_SR_AK(&t, &t, &aes_zero, false);
return t.d[HOST_BIG_ENDIAN];
}
target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)