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target/sparc: Remove cpu_fsr

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Drop this field as a tcg global, loading it explicitly in the
few places required.  This means that all FPop helpers may
once again be TCG_CALL_NO_WG.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-03 10:38:39 -07:00
parent 3590f01ed2
commit c9fa8e586b
3 changed files with 114 additions and 113 deletions
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9
target/sparc/fop_helper.c
View File

@ -344,8 +344,7 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src)
} }
#define GEN_FCMP(name, size, FS, E) \ #define GEN_FCMP(name, size, FS, E) \
target_ulong glue(helper_, name) (CPUSPARCState *env, \ void glue(helper_, name)(CPUSPARCState *env, Int128 src1, Int128 src2) \
Int128 src1, Int128 src2) \
{ \ { \
float128 reg1 = f128_in(src1); \ float128 reg1 = f128_in(src1); \
float128 reg2 = f128_in(src2); \ float128 reg2 = f128_in(src2); \
@ -376,10 +375,10 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src)
fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
break; \ break; \
} \ } \
return fsr; \ env->fsr = fsr; \
} }
#define GEN_FCMP_T(name, size, FS, E) \ #define GEN_FCMP_T(name, size, FS, E) \
target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\ void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \
{ \ { \
FloatRelation ret; \ FloatRelation ret; \
target_ulong fsr; \ target_ulong fsr; \
@ -407,7 +406,7 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src)
fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
break; \ break; \
} \ } \
return fsr; \ env->fsr = fsr; \
} }
GEN_FCMP_T(fcmps, float32, 0, 0); GEN_FCMP_T(fcmps, float32, 0, 0);

120
target/sparc/helper.h
View File

@ -36,79 +36,79 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32)
DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
#endif #endif
DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env)
DEF_HELPER_FLAGS_2(set_fsr_noftt, 0, void, env, tl) DEF_HELPER_FLAGS_2(set_fsr_noftt, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(fsqrts, 0, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_WG, f32, env, f32)
DEF_HELPER_FLAGS_2(fsqrtd, 0, f64, env, f64) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_WG, f64, env, f64)
DEF_HELPER_FLAGS_2(fsqrtq, 0, i128, env, i128) DEF_HELPER_FLAGS_2(fsqrtq, TCG_CALL_NO_WG, i128, env, i128)
DEF_HELPER_FLAGS_3(fcmps, 0, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, void, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpd, 0, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpes, 0, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, void, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmped, 0, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpq, 0, tl, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, void, env, i128, i128)
DEF_HELPER_FLAGS_3(fcmpeq, 0, tl, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, void, env, i128, i128)
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_3(fcmps_fcc1, 0, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, void, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc2, 0, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, void, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc3, 0, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, void, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpd_fcc1, 0, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpd_fcc2, 0, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpd_fcc3, 0, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpes_fcc1, 0, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, void, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpes_fcc2, 0, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, void, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpes_fcc3, 0, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, void, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmped_fcc1, 0, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped_fcc2, 0, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped_fcc3, 0, tl, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpq_fcc1, 0, tl, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128)
DEF_HELPER_FLAGS_3(fcmpq_fcc2, 0, tl, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128)
DEF_HELPER_FLAGS_3(fcmpq_fcc3, 0, tl, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128)
DEF_HELPER_FLAGS_3(fcmpeq_fcc1, 0, tl, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq_fcc1, TCG_CALL_NO_WG, void, env, i128, i128)
DEF_HELPER_FLAGS_3(fcmpeq_fcc2, 0, tl, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq_fcc2, TCG_CALL_NO_WG, void, env, i128, i128)
DEF_HELPER_FLAGS_3(fcmpeq_fcc3, 0, tl, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq_fcc3, TCG_CALL_NO_WG, void, env, i128, i128)
#endif #endif
DEF_HELPER_2(raise_exception, noreturn, env, int) DEF_HELPER_2(raise_exception, noreturn, env, int)
DEF_HELPER_FLAGS_3(faddd, 0, f64, env, f64, f64) DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fsubd, 0, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fmuld, 0, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fdivd, 0, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(faddq, 0, i128, env, i128, i128) DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_WG, i128, env, i128, i128)
DEF_HELPER_FLAGS_3(fsubq, 0, i128, env, i128, i128) DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_WG, i128, env, i128, i128)
DEF_HELPER_FLAGS_3(fmulq, 0, i128, env, i128, i128) DEF_HELPER_FLAGS_3(fmulq, TCG_CALL_NO_WG, i128, env, i128, i128)
DEF_HELPER_FLAGS_3(fdivq, 0, i128, env, i128, i128) DEF_HELPER_FLAGS_3(fdivq, TCG_CALL_NO_WG, i128, env, i128, i128)
DEF_HELPER_FLAGS_3(fadds, 0, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsubs, 0, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fmuls, 0, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fdivs, 0, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsmuld, 0, f64, env, f32, f32) DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_WG, f64, env, f32, f32)
DEF_HELPER_FLAGS_3(fdmulq, 0, i128, env, f64, f64) DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_WG, i128, env, f64, f64)
DEF_HELPER_FLAGS_2(fitod, 0, f64, env, s32) DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_WG, f64, env, s32)
DEF_HELPER_FLAGS_2(fitoq, 0, i128, env, s32) DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_WG, i128, env, s32)
DEF_HELPER_FLAGS_2(fitos, 0, f32, env, s32) DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_WG, f32, env, s32)
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_2(fxtos, 0, f32, env, s64) DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_WG, f32, env, s64)
DEF_HELPER_FLAGS_2(fxtod, 0, f64, env, s64) DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_WG, f64, env, s64)
DEF_HELPER_FLAGS_2(fxtoq, 0, i128, env, s64) DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_WG, i128, env, s64)
#endif #endif
DEF_HELPER_FLAGS_2(fdtos, 0, f32, env, f64) DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_WG, f32, env, f64)
DEF_HELPER_FLAGS_2(fstod, 0, f64, env, f32) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_WG, f64, env, f32)
DEF_HELPER_FLAGS_2(fqtos, 0, f32, env, i128) DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_WG, f32, env, i128)
DEF_HELPER_FLAGS_2(fstoq, 0, i128, env, f32) DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_WG, i128, env, f32)
DEF_HELPER_FLAGS_2(fqtod, 0, f64, env, i128) DEF_HELPER_FLAGS_2(fqtod, TCG_CALL_NO_WG, f64, env, i128)
DEF_HELPER_FLAGS_2(fdtoq, 0, i128, env, f64) DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_WG, i128, env, f64)
DEF_HELPER_FLAGS_2(fstoi, 0, s32, env, f32) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_WG, s32, env, f32)
DEF_HELPER_FLAGS_2(fdtoi, 0, s32, env, f64) DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_WG, s32, env, f64)
DEF_HELPER_FLAGS_2(fqtoi, 0, s32, env, i128) DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_WG, s32, env, i128)
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_2(fstox, 0, s64, env, f32) DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_WG, s64, env, f32)
DEF_HELPER_FLAGS_2(fdtox, 0, s64, env, f64) DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_WG, s64, env, f64)
DEF_HELPER_FLAGS_2(fqtox, 0, s64, env, i128) DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128)
DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64)

98
target/sparc/translate.c
View File

@ -99,7 +99,7 @@
/* global register indexes */ /* global register indexes */
static TCGv_ptr cpu_regwptr; static TCGv_ptr cpu_regwptr;
static TCGv cpu_fsr, cpu_pc, cpu_npc; static TCGv cpu_pc, cpu_npc;
static TCGv cpu_regs[32]; static TCGv cpu_regs[32];
static TCGv cpu_y; static TCGv cpu_y;
static TCGv cpu_tbr; static TCGv cpu_tbr;
@ -1097,7 +1097,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond) static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
{ {
unsigned int offset; unsigned int offset;
TCGv r_dst; TCGv r_dst, fsr;
/* For now we still generate a straight boolean result. */ /* For now we still generate a straight boolean result. */
cmp->cond = TCG_COND_NE; cmp->cond = TCG_COND_NE;
@ -1120,54 +1120,56 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
break; break;
} }
fsr = tcg_temp_new();
tcg_gen_ld_tl(fsr, tcg_env, offsetof(CPUSPARCState, fsr));
switch (cond) { switch (cond) {
case 0x0: case 0x0:
gen_op_eval_bn(r_dst); gen_op_eval_bn(r_dst);
break; break;
case 0x1: case 0x1:
gen_op_eval_fbne(r_dst, cpu_fsr, offset); gen_op_eval_fbne(r_dst, fsr, offset);
break; break;
case 0x2: case 0x2:
gen_op_eval_fblg(r_dst, cpu_fsr, offset); gen_op_eval_fblg(r_dst, fsr, offset);
break; break;
case 0x3: case 0x3:
gen_op_eval_fbul(r_dst, cpu_fsr, offset); gen_op_eval_fbul(r_dst, fsr, offset);
break; break;
case 0x4: case 0x4:
gen_op_eval_fbl(r_dst, cpu_fsr, offset); gen_op_eval_fbl(r_dst, fsr, offset);
break; break;
case 0x5: case 0x5:
gen_op_eval_fbug(r_dst, cpu_fsr, offset); gen_op_eval_fbug(r_dst, fsr, offset);
break; break;
case 0x6: case 0x6:
gen_op_eval_fbg(r_dst, cpu_fsr, offset); gen_op_eval_fbg(r_dst, fsr, offset);
break; break;
case 0x7: case 0x7:
gen_op_eval_fbu(r_dst, cpu_fsr, offset); gen_op_eval_fbu(r_dst, fsr, offset);
break; break;
case 0x8: case 0x8:
gen_op_eval_ba(r_dst); gen_op_eval_ba(r_dst);
break; break;
case 0x9: case 0x9:
gen_op_eval_fbe(r_dst, cpu_fsr, offset); gen_op_eval_fbe(r_dst, fsr, offset);
break; break;
case 0xa: case 0xa:
gen_op_eval_fbue(r_dst, cpu_fsr, offset); gen_op_eval_fbue(r_dst, fsr, offset);
break; break;
case 0xb: case 0xb:
gen_op_eval_fbge(r_dst, cpu_fsr, offset); gen_op_eval_fbge(r_dst, fsr, offset);
break; break;
case 0xc: case 0xc:
gen_op_eval_fbuge(r_dst, cpu_fsr, offset); gen_op_eval_fbuge(r_dst, fsr, offset);
break; break;
case 0xd: case 0xd:
gen_op_eval_fble(r_dst, cpu_fsr, offset); gen_op_eval_fble(r_dst, fsr, offset);
break; break;
case 0xe: case 0xe:
gen_op_eval_fbule(r_dst, cpu_fsr, offset); gen_op_eval_fbule(r_dst, fsr, offset);
break; break;
case 0xf: case 0xf:
gen_op_eval_fbo(r_dst, cpu_fsr, offset); gen_op_eval_fbo(r_dst, fsr, offset);
break; break;
} }
} }
@ -1264,16 +1266,16 @@ static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
{ {
switch (fccno) { switch (fccno) {
case 0: case 0:
gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmps(tcg_env, r_rs1, r_rs2);
break; break;
case 1: case 1:
gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmps_fcc1(tcg_env, r_rs1, r_rs2);
break; break;
case 2: case 2:
gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmps_fcc2(tcg_env, r_rs1, r_rs2);
break; break;
case 3: case 3:
gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmps_fcc3(tcg_env, r_rs1, r_rs2);
break; break;
} }
} }
@ -1282,16 +1284,16 @@ static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
{ {
switch (fccno) { switch (fccno) {
case 0: case 0:
gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpd(tcg_env, r_rs1, r_rs2);
break; break;
case 1: case 1:
gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpd_fcc1(tcg_env, r_rs1, r_rs2);
break; break;
case 2: case 2:
gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpd_fcc2(tcg_env, r_rs1, r_rs2);
break; break;
case 3: case 3:
gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpd_fcc3(tcg_env, r_rs1, r_rs2);
break; break;
} }
} }
@ -1300,16 +1302,16 @@ static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
{ {
switch (fccno) { switch (fccno) {
case 0: case 0:
gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpq(tcg_env, r_rs1, r_rs2);
break; break;
case 1: case 1:
gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpq_fcc1(tcg_env, r_rs1, r_rs2);
break; break;
case 2: case 2:
gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpq_fcc2(tcg_env, r_rs1, r_rs2);
break; break;
case 3: case 3:
gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpq_fcc3(tcg_env, r_rs1, r_rs2);
break; break;
} }
} }
@ -1318,16 +1320,16 @@ static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
{ {
switch (fccno) { switch (fccno) {
case 0: case 0:
gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpes(tcg_env, r_rs1, r_rs2);
break; break;
case 1: case 1:
gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpes_fcc1(tcg_env, r_rs1, r_rs2);
break; break;
case 2: case 2:
gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpes_fcc2(tcg_env, r_rs1, r_rs2);
break; break;
case 3: case 3:
gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpes_fcc3(tcg_env, r_rs1, r_rs2);
break; break;
} }
} }
@ -1336,16 +1338,16 @@ static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
{ {
switch (fccno) { switch (fccno) {
case 0: case 0:
gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmped(tcg_env, r_rs1, r_rs2);
break; break;
case 1: case 1:
gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmped_fcc1(tcg_env, r_rs1, r_rs2);
break; break;
case 2: case 2:
gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmped_fcc2(tcg_env, r_rs1, r_rs2);
break; break;
case 3: case 3:
gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmped_fcc3(tcg_env, r_rs1, r_rs2);
break; break;
} }
} }
@ -1354,16 +1356,16 @@ static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
{ {
switch (fccno) { switch (fccno) {
case 0: case 0:
gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2);
break; break;
case 1: case 1:
gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpeq_fcc1(tcg_env, r_rs1, r_rs2);
break; break;
case 2: case 2:
gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpeq_fcc2(tcg_env, r_rs1, r_rs2);
break; break;
case 3: case 3:
gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpeq_fcc3(tcg_env, r_rs1, r_rs2);
break; break;
} }
} }
@ -1372,32 +1374,32 @@ static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
{ {
gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmps(tcg_env, r_rs1, r_rs2);
} }
static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
{ {
gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpd(tcg_env, r_rs1, r_rs2);
} }
static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) static void gen_op_fcmpq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
{ {
gen_helper_fcmpq(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpq(tcg_env, r_rs1, r_rs2);
} }
static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
{ {
gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpes(tcg_env, r_rs1, r_rs2);
} }
static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
{ {
gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmped(tcg_env, r_rs1, r_rs2);
} }
static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2) static void gen_op_fcmpeq(int fccno, TCGv_i128 r_rs1, TCGv_i128 r_rs2)
{ {
gen_helper_fcmpeq(cpu_fsr, tcg_env, r_rs1, r_rs2); gen_helper_fcmpeq(tcg_env, r_rs1, r_rs2);
} }
#endif #endif
@ -4413,8 +4415,9 @@ static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop,
tnew = tcg_temp_new(); tnew = tcg_temp_new();
told = tcg_temp_new(); told = tcg_temp_new();
tcg_gen_qemu_ld_tl(tnew, addr, dc->mem_idx, mop | MO_ALIGN); tcg_gen_qemu_ld_tl(tnew, addr, dc->mem_idx, mop | MO_ALIGN);
tcg_gen_ld_tl(told, tcg_env, offsetof(CPUSPARCState, fsr));
tcg_gen_andi_tl(tnew, tnew, new_mask); tcg_gen_andi_tl(tnew, tnew, new_mask);
tcg_gen_andi_tl(told, cpu_fsr, old_mask); tcg_gen_andi_tl(told, told, old_mask);
tcg_gen_or_tl(tnew, tnew, told); tcg_gen_or_tl(tnew, tnew, told);
gen_helper_set_fsr_noftt(tcg_env, tnew); gen_helper_set_fsr_noftt(tcg_env, tnew);
return advance_pc(dc); return advance_pc(dc);
@ -5342,7 +5345,6 @@ void sparc_tcg_init(void)
{ &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" }, { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" },
{ &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" }, { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" },
{ &cpu_cond, offsetof(CPUSPARCState, cond), "cond" }, { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
{ &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
{ &cpu_pc, offsetof(CPUSPARCState, pc), "pc" }, { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
{ &cpu_npc, offsetof(CPUSPARCState, npc), "npc" }, { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
{ &cpu_y, offsetof(CPUSPARCState, y), "y" }, { &cpu_y, offsetof(CPUSPARCState, y), "y" },