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target/sparc: Implement CMASK instructions

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-04 12:55:49 -07:00
parent 015fc6fcdb
commit c973b4e8df
4 changed files with 58 additions and 0 deletions
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3
target/sparc/helper.h
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@ -107,6 +107,9 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmask8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#define VIS_CMPHELPER(name) \
DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \

4
target/sparc/insns.decode
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@ -384,6 +384,10 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r
CMASK8 10 00000 110110 00000 0 0001 1011 rs2:5
CMASK16 10 00000 110110 00000 0 0001 1101 rs2:5
CMASK32 10 00000 110110 00000 0 0001 1111 rs2:5
FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_d_d
FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_d_d
FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_d_d

13
target/sparc/translate.c
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@ -61,6 +61,9 @@
# define gen_helper_write_softint(E, S) qemu_build_not_reached()
# define gen_helper_wrpil(E, S) qemu_build_not_reached()
# define gen_helper_wrpstate(E, S) qemu_build_not_reached()
# define gen_helper_cmask8 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_cmask16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_cmask32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL; })
@ -3748,6 +3751,16 @@ static void gen_op_bmask(TCGv dst, TCGv s1, TCGv s2)
TRANS(BMASK, VIS2, do_rrr, a, gen_op_bmask)
static bool do_cmask(DisasContext *dc, int rs2, void (*func)(TCGv, TCGv, TCGv))
{
func(cpu_gsr, cpu_gsr, gen_load_gpr(dc, rs2));
return true;
}
TRANS(CMASK8, VIS3, do_cmask, a->rs2, gen_helper_cmask8)
TRANS(CMASK16, VIS3, do_cmask, a->rs2, gen_helper_cmask16)
TRANS(CMASK32, VIS3, do_cmask, a->rs2, gen_helper_cmask32)
static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
{
TCGv dst, src1, src2;

38
target/sparc/vis_helper.c
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@ -351,3 +351,41 @@ uint64_t helper_bshuffle(uint64_t gsr, uint64_t src1, uint64_t src2)
return r.ll;
}
uint64_t helper_cmask8(uint64_t gsr, uint64_t src)
{
uint32_t mask = 0;
mask |= (src & 0x01 ? 0x00000007 : 0x0000000f);
mask |= (src & 0x02 ? 0x00000060 : 0x000000e0);
mask |= (src & 0x04 ? 0x00000500 : 0x00000d00);
mask |= (src & 0x08 ? 0x00004000 : 0x0000c000);
mask |= (src & 0x10 ? 0x00030000 : 0x000b0000);
mask |= (src & 0x20 ? 0x00200000 : 0x00a00000);
mask |= (src & 0x40 ? 0x01000000 : 0x09000000);
mask |= (src & 0x80 ? 0x00000000 : 0x80000000);
return deposit64(gsr, 32, 32, mask);
}
uint64_t helper_cmask16(uint64_t gsr, uint64_t src)
{
uint32_t mask = 0;
mask |= (src & 0x1 ? 0x00000067 : 0x000000ef);
mask |= (src & 0x2 ? 0x00004500 : 0x0000cd00);
mask |= (src & 0x4 ? 0x00230000 : 0x00ab0000);
mask |= (src & 0x8 ? 0x01000000 : 0x89000000);
return deposit64(gsr, 32, 32, mask);
}
uint64_t helper_cmask32(uint64_t gsr, uint64_t src)
{
uint32_t mask = 0;
mask |= (src & 0x1 ? 0x00004567 : 0x0000cdef);
mask |= (src & 0x2 ? 0x01230000 : 0x89ab0000);
return deposit64(gsr, 32, 32, mask);
}